| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel |
| 2019-01-23 | RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y | Vincent Chen |
| 2019-01-07 | riscv: add audit support | David Abdurachmanov |
| 2018-10-22 | RISC-V: SMP cleanup and new features | Palmer Dabbelt |
| 2018-10-22 | RISC-V: No need to pass scause as arg to do_IRQ() | Anup Patel |
| 2018-10-22 | Extract FPU context operations from entry.S | Alan Kao |
| 2018-08-13 | RISC-V: implement low-level interrupt handling | Christoph Hellwig |
| 2018-03-14 | RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler | Palmer Dabbelt |
| 2018-02-20 | RISC-V: Enable IRQ during exception handling | zongbox@gmail.com |
| 2018-01-30 | riscv: disable SUM in the exception handler | Christoph Hellwig |
| 2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig |
| 2017-09-26 | RISC-V: Task implementation | Palmer Dabbelt |
 |
index : lwn.git | |
| Linux kernel documentation tree maintained by Jonathan Corbet |
| summaryrefslogtreecommitdiff |