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2023-04-07arm64: dts: qcom: sc7280: Fix up the gic nodeKonrad Dybcio
Fix the following schema warning: gic-its@17a40000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'msi-controller': True, '#msi-cells': [[1]], 'reg': [[0, 396623872, 0, 131072]], 'status': ['disabled']} And reorder the properties to be more in order with all other nodes. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-4-6efb4196f51f@linaro.org
2023-04-07arm64: dts: qcom: sc7280: Fix qspi pin configDouglas Anderson
Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config")), we should adjust the qspi pin config for sc7280. I won't re-describe all the research/arguments in the sc7180 patch here, but there are a few differences for sc7280 worth noting: 1. On herobrine the SPI flash (qspi) is wired up differently on the board. Rather than Cr50 and the AP being wired directly together, there's actually a mux that will _either_ connect the AP to the flash or Cr50 to the flash. This means that the internal pulls on Cr50 don't affect us and we should enable our own pulldowns. 2. On herobrine, EEs added an external pulldown on the MISO line. The argument in the schematic said that we added it (but not one on MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and CLK. ...though, as per #1, those Cr50 pulldowns would only affect the line when the mux was swung to Cr50. The ironic result of #1 and #2 is that the external pulldowns on CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on trogdor. 3. While I still don't have the actual exact schematics for all variants of IDP/CRD that were produced, I have some reference schematics that give me a belief of how the qspi is hooked up there. From this, I'm fairly certain that all of the older variants of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe through a direct connect to Cr50) or have no pull (in other words, they don't have a pullup). I'll go ahead and enable internal pulldowns on all the lines since that won't hurt to double-pull if there's an external pulldown and it's nice to have a pulldown if there's nothing external. Note that this only affects _older_ CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin device trees). 4. I didn't find the same strange "auto-switch-to-keeper" at suspend when probing on sc7280. Whatever pulls (or lack thereof) I left at suspend time seemed to persist into suspend. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid
2023-04-07arm64: dts: sc7280: Rename qspi data12 as data23Douglas Anderson
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: 7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node") Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid
2023-04-06arm64: dts: qcom: Remove "iommus" property from PCIe nodesManivannan Sadhasivam
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
2023-04-04arm64: dts: qcom: sc7280: Use the correct BWMON fallback compatibleKonrad Dybcio
Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org
2023-03-28Merge branch 'arm64-fixes-for-6.3' into arm64-for-6.4Bjorn Andersson
Merge the arm64-fixes-for-6.3 branch to avoid merge conflicts with changes for v6.4.
2023-03-21arm64: dts: qcom: drop redundant line breaksKrzysztof Kozlowski
Remove trailing, redundant line breaks. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org
2023-03-15arm64: dts: qcom: sc7280: Fix the PCI I/O port rangeManivannan Sadhasivam
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reported-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230228164752.55682-4-manivannan.sadhasivam@linaro.org
2023-03-15arm64: dts: qcom: sc7280: fix EUD port propertiesKrzysztof Kozlowski
Nodes with unit addresses must have also 'reg' property: sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property Fixes: 0b059979090d ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org
2023-03-15arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banksManivannan Sadhasivam
The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org
2023-03-14arm64: dts: qcom: sc7280: Add qcom,smmu-500 to Adreno SMMUKonrad Dybcio
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230216145646.4095336-2-konrad.dybcio@linaro.org
2023-03-14arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUsManivannan Sadhasivam
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org
2023-03-06arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherentKrishna chaitanya chundru
If the controller is not marked as cache coherent, then kernel will try to ensure coherency during dma-ops and that may cause data corruption. So, mark the PCIe node as dma-coherent as the devices on PCIe bus are cache coherent. Cc: stable@vger.kernel.org Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related node") Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1677584952-17496-1-git-send-email-quic_krichai@quicinc.com
2023-01-18arm64: dts: qcom: sc7280: Pad addresses to 8 hex digitsKonrad Dybcio
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-14-konrad.dybcio@linaro.org
2023-01-16arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpointKuogee Hsieh
Move data-lanes property from mdss_dp node to dp_out endpoint. Also add link-frequencies property into dp_out endpoint as well. The last frequency specified at link-frequencies will be the max link rate supported by DP. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1672163103-31254-2-git-send-email-quic_khsieh@quicinc.com
2023-01-10arm64: dts: qcom: rename AOSS QMP nodesKrzysztof Kozlowski
The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 135780456218 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is now handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "power-management". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: sc7280: correct SPMI bus address cellsKrzysztof Kozlowski
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 14abf8dfe364 ("arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213101921.47924-2-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: sc7280: Fix CPU nodes compatible stringRob Herring
'arm,kryo' is not documented and is not an Arm Ltd thing either as that is Qualcomm branding. The correct compatible is 'qcom,kryo'. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221207211327.2848665-1-robh@kernel.org
2022-12-29arm64: dts: qcom: sc7280: Add compat qcom,sc7280-dsi-ctrlBryan O'Donoghue
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sc7280 against the yaml documentation. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221223021025.1646636-15-bryan.odonoghue@linaro.org
2022-12-29arm64: dts: qcom: Update cache propertiesPierre Gondois
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> [bjorn: Moved "qcom" to $subject prefix] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
2022-12-28arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support nodeSouradeep Chowdhury
Add the DCC(Data Capture and Compare) device tree node entry along with the address of the register region. Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/88ef6053ee56eb0613040ea1fe33439934810330.1672148732.git.quic_schowdhu@quicinc.com
2022-12-27arm64: dts: qcom: sc7280: align MPSS PAS node with bindingsKrzysztof Kozlowski
The SC7180 MPSS/MSS remote processor can be brought to life using two different bindings: 1. qcom,sc7280-mpss-pas - currently used in DTSI 2. qcom,sc7280-mss-pil Move the properties related to qcom,sc7180-mss-pil (qcom,halt-regs, qcom,ext-regs, qcom,qaccept-regs, resets and additional clocks) to specific board using the PIL, to silence DT schema warnings. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221124184333.133911-5-krzysztof.kozlowski@linaro.org
2022-12-06arm64: dts: qcom: sc7280: Remove unused sleep pin control nodesSrinivasa Rao Mandadapu
Remove unused and redundant sleep pin control entries as they are not referenced anywhere in sc7280 based platform's device tree variants. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reported-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1668591184-21099-1-git-send-email-quic_srivasam@quicinc.com
2022-12-06arm64: dts: qcom: Align with generic osm-l3/epss-l3Bjorn Andersson
Update all references to OSM or EPSS L3 compatibles, to include the generic compatible, as defined by the updated binding. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-7-quic_bjorande@quicinc.com
2022-12-02Merge branch 'arm64-fixes-for-6.1' into HEADBjorn Andersson
Mergeback arm64-fixes-for-6.1 to avoid merge conflicts.
2022-11-09arm64: dts: qcom: sc7280: Remove redundant soundwire propertySrinivasa Rao Mandadapu
Remove redundant and undocumented property qcom,port-offset in soundwire controller nodes. This patch is required to avoid dtbs_check errors with qcom,soundwire.yaml Fixes: 12ef689f09ab ("arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1667918763-32445-4-git-send-email-quic_srivasam@quicinc.com
2022-11-07arm64: dts: qcom: sc7280: Add nodes to support WoW on WCN6750Manikanta Pubbisetty
Add DT nodes to support WoW (Wake on Wireless) feature on WCN6750 WiFi hardware on SC7280 SoC. Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221017125346.3691-3-quic_mpubbise@quicinc.com
2022-11-05arm64: dts: qcom: sc7280: Add GPI DMA compatible fallbackKrzysztof Kozlowski
Use SM6350 as fallback for GPI DMA, to indicate devices are compatible and that drivers can bind with only one compatible. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018230352.1238479-4-krzysztof.kozlowski@linaro.org
2022-11-05arm64: dts: qcom: sc7280: align LPASS pin configuration with DT schemaKrzysztof Kozlowski
DT schema expects LPASS pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-3-krzysztof.kozlowski@linaro.org
2022-11-05arm64: dts: qcom: sc7280: drop clock-cells from LPASS TLMMKrzysztof Kozlowski
The LPASS pin-controller is not a clock provider: qcom/sc7280-herobrine-herobrine-r1.dtb: pinctrl@33c0000: '#clock-cells' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-2-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: sc7280: Fix cpufreq-epss compatibleLuca Weiss
The bindings require a SoC-specific compatible to be used next to qcom,cpufreq-epss. Add it to make dtbs_check happy. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221016090035.565350-2-luca@z3ntu.xyz
2022-10-17arm64: dts: qcom: sc7280: assign DSI clock source parentsRajeev Nandan
Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662550553-28933-1-git-send-email-quic_rajeevny@quicinc.com
2022-10-17arm64: dts: qcom: sc7280: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sc7280 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-8-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sc7280: Add the reset reg for lpass audiocc on SC7280Satya Priya
Add the reset register offset for clock gating. Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663674495-25748-1-git-send-email-quic_c_skakit@quicinc.com
2022-10-17arm64: dts: qcom: sc7280: Add required-opps for i2cRajendra Nayak
qup-i2c devices on sc7280 are clocked with a fixed clock (19.2 MHz) Though qup-i2c does not support DVFS, it still needs to vote for a performance state on 'CX' to satisfy the 19.2 Mhz clock frequency requirement. Use 'required-opps' to pass this information from device tree, and also add the power-domains property to specify the CX power-domain. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927104233.29376-1-quic_rjendra@quicinc.com
2022-10-17arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema (really)Krzysztof Kozlowski
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. I already tried to do this in commit d801357a0573 ("arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema") and I missed the fact that these nodes were not part of "state" node. Bindings did not catch these errors due to its own issues. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-5-krzysztof.kozlowski@linaro.org
2022-10-06Merge tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM devicetree updates from Arnd Bergmann: "Most of the changes fall into one of three categories: adding support for additional devices on existing machines, cleaning up issues found by the ongoing conversion to machine-readable bindings, and addressing minor mistakes in the existing DT data. Across SoC vendors, Qualcomm and Freescale stick out as getting the most updates, which corresponds to their dominance in the mobile phone and embedded industrial markets, respectively. There are 636 non-merge changeset in this branch, which is a little lower than most times, but more importantly we only add 36 machine files, which is about half of what we had the past few releases. Eight new SoCs are added, but all of them are variations of already supported SoC families, and most of them come with one reference board design from the SoC vendor: - Mediatek MT8186 is a Chromebook/Tablet type SoC, similar to the MT65xx series of phone SoCs, with two Cortex-A76 and six Cortex-A55 cores. - TI AM62A is another member of the K3 family with Cortex-A53 cores, this one is targetted at Video/Vision processing for industrial and automotive applications. - NXP i.MX8DXL is another chip for this market in the ever-growing i.MX8 family, this one again with two Cortex-A35 cores. - Renesas R-Car H3Ne-1.7G (R8A779MB) and R-Car V3H2 (R8A77980A) are minor updates of R8A77951 and R8A77980, respectively. - Qualcomm IPQ8064-v2.0, IPQ8062 and IPQ8065 are all variants of the IPQ8064 chip, with minimally different features. The AMD Pensando Elba and Apple M1 Ultra SoC support was getting close this time, but in the end did not make the cut. The new machines based on existing SoC support are fairly uneventful: - Sony Xperia 1 IV is a fairly recent phone based on Qualcomm Snapdragon 8 Gen 1. - Three Samsung phones based on Snapdragon 410: Galaxy E5, E7 and Grand Max. These are added for both 32-bit and 64-bit kernels, as they originally shipped running 32-bit code. - Two new servers using AST2600 BMCs: AMD DaytonaX and Ampere Mt. Mitchell - Three new machines based on Rockchips RK3399 and RK3566: Anberic RG353P and RG503, Pine64 Pinephone Pro, Open AI Lab - Multiple NXP i.MX6/i.MX8 based boards: Kontron SL/BL i.MX8MM OSM-S, i.MX8MM Gateworks GW7904, MSC SM2S-IMX8PLUS SoM and carrier board - Two development boards in the Microchip AT91 family: SAMA5D3-EDS and lan966x-pcb8290. - Minor variants of existing boards using Amlogic, Broadcom, Marvell, Rockchips, Freescale Layerscape and Socionext Uniphier SoCs" * tag 'arm-dt-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (617 commits) Revert "ARM: dts: BCM5301X: Add basic PCI controller properties" ARM: dts: s5pv210: correct double "pins" in pinmux node ARM: dts: exynos: fix polarity of VBUS GPIO of Origen arm64: dts: exynos: fix polarity of "enable" line of NFC chip in TM2 arm64: dts: uniphier: Add L2 cache node arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node arm64: dts: uniphier: Fix opp-table node name for LD20 arm64: dts: uniphier: Add USB-device support for PXs3 reference board arm64: dts: uniphier: Add ahci controller nodes for PXs3 arm64: dts: uniphier: Use GIC interrupt definitions arm64: dts: uniphier: Rename gpio-hog nodes arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller arm64: dts: uniphier: Rename pvtctl node to thermal-sensor ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card ARM: dts: uniphier: Add ahci controller nodes for PXs2 ARM: dts: uniphier: Add ahci controller nodes for Pro4 ARM: dts: uniphier: Use GIC interrupt definitions ARM: dts: uniphier: Rename gpio-hog node ...
2022-09-16arm64: dts: qcom: sc7280: Add required-opps for USBRajendra Nayak
USB has a requirement to put a performance state vote on 'cx' while active. Use 'required-opps' to pass this information from device tree, and since all the GDSCs in GCC (including USB) are sub-domains of cx, we also add cx as a power-domain for GCC. Now when any of the consumers of the GDSCs (in this case USB) votes on a perforamance state, genpd framework can identify that the GDSC itself does not support a performance state and it then propogates the vote to the parent, which in this case is cx. This change would also mean that any GDSC in GCC thats left enabled during low power state (perhaps because its marked with a ALWAYS_ON flag) can prevent the system from entering low power since that would prevent cx from transitioning to low power. Ideally any consumers that would need to have their devices (partially) powered to support wakeups should look at making the resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead of leaving them ALWAYS_ON. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220916103124.30581-1-quic_rjendra@quicinc.com
2022-09-14arm64: dts: qcom: sc7280: Add missing aggre0, aggre1 clocksKrishna chaitanya chundru
Add missing aggre0, aggre1 clocks. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662626776-19636-2-git-send-email-quic_krichai@quicinc.com
2022-09-13arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schemaKrzysztof Kozlowski
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220912061746.6311-40-krzysztof.kozlowski@linaro.org
2022-09-13arm64: dts: qcom: sc7280: Add lpass cpu nodeSrinivasa Rao Mandadapu
Add lpass cpu node for audio on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1657200184-29565-9-git-send-email-quic_srivasam@quicinc.com
2022-09-13arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro ↵Srinivasa Rao Mandadapu
codecs SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with external codecs using soundwire masters. Add these nodes for sc7280 based platforms audio use case. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1657200184-29565-2-git-send-email-quic_srivasam@quicinc.com
2022-09-08arm64: dts: qcom: sc7280: correct CPU BWMON unit addressKrzysztof Kozlowski
Correct CPU BWMON unit address to match the "reg" property. Reported-by: Stephen Boyd <swboyd@chromium.org> Fixes: b2f3eac1b77c ("arm64: dts: qcom: sc7280: Add cpu and llcc BWMON") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908085830.39141-1-krzysztof.kozlowski@linaro.org
2022-09-05arm64: dts: qcom: fix syscon node namesJohan Hovold
Some recent changes that added new syscon nodes used misspelled node names. Fixes: 86d7c9460e2c arm64: dts: qcom: sm8150: split TCSR halt regs out of mutex Fixes: 0da603387225 arm64: dts: qcom: sdm630: split TCSR halt regs out of mutex Fixes: 8a8531e69b2d arm64: dts: qcom: sdm845: split TCSR halt regs out of mutex Fixes: d9a2214d6ba5 arm64: dts: qcom: sc7280: split TCSR halt regs out of mutex Fixes: ce1ac53c7faa arm64: dts: qcom: sc7180: split TCSR halt regs out of mutex Fixes: fc10cfa38580 arm64: dts: qcom: msm8998: split TCSR halt regs out of mutex Fixes: 100ce2205924 arm64: dts: qcom: msm8996: split TCSR halt regs out of mutex Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220905091602.20364-1-johan+linaro@kernel.org
2022-09-05arm64: dts: qcom: sc7280: Add cpu and llcc BWMONRajendra Nayak
Add cpu and llcc BWMON nodes and their corresponding OPP tables for sc7280 SoC. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220902043511.17130-5-quic_rjendra@quicinc.com
2022-08-29arm64: dts: qcom: sc7280: Update gpu opp tableAkhil P Oommen
On the lite sku where GPU Fmax is 550Mhz, voting for a slightly higher bandwidth at the highest gpu opp helps to improve "Manhattan offscreen" score by 10%. Update the gpu opp table such that this is applicable only on SKUs which has 550Mhz as GPU Fmax. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220829011035.1.Ie3564662150e038571b7e2779cac7229191cf3bf@changeid
2022-08-29arm64: dts: qcom: sc7280: move USB wakeup-source propertyJohan Hovold
Move the USB-controller wakeup-source property to the dwc3 glue node to match the updated binding. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220802152642.2516-1-johan+linaro@kernel.org
2022-08-29arm64: dts: qcom: sc7280: Update lpasscore nodeSatya Priya
To maintain consistency with other lpass nodes(lpass_audiocc, lpass_aon and lpass_hm), update lpasscore to lpass_core. Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-4-git-send-email-quic_c_skakit@quicinc.com
2022-08-29arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resetsTaniya Das
The lpass audio supports TX/RX/WSA block resets. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-3-git-send-email-quic_c_skakit@quicinc.com
2022-08-29arm64: dts: qcom: sc7280: Cleanup the lpasscc nodeSatya Priya
Remove "cc" regmap from lpasscc node which is overlapping with the lpass_aon regmap. Fixes: 422a295221bb ("arm64: dts: qcom: sc7280: Add clock controller nodes") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1660107909-27947-2-git-send-email-quic_c_skakit@quicinc.com