| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-08-16 | ARM: cache: add extra feature enable for tauros2 | Chao Xie | |
| The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> | |||
| 2009-11-27 | ARM: Add Tauros2 L2 cache controller support | Lennert Buytenhek | |
| Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> | |||
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