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Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.
This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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"aes1_fck" and "aes2_fck" are controlled by hwmod. Drop clock
entries to avoid conflicts.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The IVA DPLL is not an essential DPLL for the functionality of a
bootloader and is usually not configured (e.g. older u-boots configure
it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
than 2014.01 do not even have an option), and this results in incorrect
operating frequencies when trying to use a DSP or IVAHD, whose root
clocks are derived from this DPLL. Use the DT standard properties
"assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
rate and the rates for its derivative clocks at boot time to properly
initialize/lock this DPLL. The DPLL will automatically transition
into a low-power stop mode when the associated output clocks are
not utilized or gated automatically.
The reset values of the dividers M4 & M5 (functional clocks for DSP and
IVAHD respectively) are identical to each other, but are different at
each OPP. The reset values also do not match a specific OPP. So, the
derived output clocks from the IVA DPLL have to be initialized as well
to avoid initializing these divider outputs to incorrect frequencies.
The clock rates are chosen based on the OPP100 values as defined in the
OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred
Settings". The DPLL locked frequency is 1862.4 MHz (value for
DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of
this value.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP4 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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"dss_fck" is a hacky clock, used to work around problems with MODULEMODE
bit handling in DSS hwmods.
These problems have now been solved, so we can remove the dss_fck clock.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit.taneja@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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