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path: root/arch/arc/include/asm/arcregs.h
AgeCommit message (Expand)Author
2019-02-21ARCv2: don't assume core 0x54 has dual issueVineet Gupta
2019-01-17ARC: boot log: print Action point detailsVineet Gupta
2019-01-17ARCv2: boot log: BPU return stack depthVineet Gupta
2017-11-13ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop BufferVineet Gupta
2017-10-03ARCv2: boot log: identify HS48 cores (dual issue)Vineet Gupta
2017-10-03ARC: boot log: decontaminate ARCv2 ISA_CONFIG registerVineet Gupta
2017-02-06ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 regYuriy Kolerov
2016-12-19ARC: mm: No need to save cache version in @cpuinfoVineet Gupta
2016-11-30ARC: breakout timer include code into separate header ...Vineet Gupta
2016-11-30ARC: breakout aux handling into a separate headerVineet Gupta
2016-11-07ARC: change return value of userspace cmpxchg assist syscallVineet Gupta
2016-10-28ARC: boot log: refactor cpu name/release printingVineet Gupta
2016-10-28ARC: boot log: don't assume SWAPE instruction supportVineet Gupta
2016-10-28ARC: boot log: refactor printing abt features not captured in BCRsVineet Gupta
2016-09-30ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta
2016-03-12ARC: build: Better way to detect ISA compatible toolchainVineet Gupta
2016-02-18ARCv2: boot report CCMs (Closely Coupled Memories)Vineet Gupta
2016-01-29ARC: shrink cpuinfo by not saving full timer BCRVineet Gupta
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta
2015-10-17ARC: make write_aux_reg safer against macro substitutionVineet Gupta
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin
2015-08-03ARCv2: Fix the peripheral address space detectionVineet Gupta
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta
2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta
2015-06-22ARCv2: [intc] HS38 core interrupt controllerVineet Gupta
2015-06-22ARC: uncached base is hard constant for ARC, don't save itVineet Gupta
2015-06-19ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta
2015-06-19ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta
2015-04-13ARC: Fix RTT boot printingVineet Gupta
2015-04-13ARC: cosmetic: Remove unused ECR bitfield masksVineet Gupta
2015-04-13ARC: Fix WRITE_BCRVineet Gupta
2014-10-13ARC: boot: cpu feature print enhancementsVineet Gupta
2014-10-13ARC: unbork FPU save/restoreVineet Gupta
2014-10-13ARC: remove extraneous __KERNEL__ guardsVineet Gupta
2014-07-23ARC: cache boot reporting updatesVineet Gupta
2013-06-26ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta
2013-06-22ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta
2013-06-22ARC: cache detection code bitrotVineet Gupta
2013-06-22ARC: Disintegrate arcregs.hVineet Gupta
2013-02-15ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta
2013-02-15ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta
2013-02-15ARC: MMU Exception HandlingVineet Gupta
2013-02-15ARC: MMU Context ManagementVineet Gupta
2013-02-15ARC: Cache Flush ManagementVineet Gupta
2013-02-11ARC: Timers/counters/delay managementVineet Gupta
2013-02-11ARC: Process-creation/scheduling/idle-loopVineet Gupta
2013-02-11ARC: Interrupt HandlingVineet Gupta
2013-02-11ARC: irqflags - Interrupt enabling/disabling at in-core intcVineet Gupta