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AgeCommit message (Expand)Author
2019-07-12drm/i915: Add test for invalid flag bits in whitelist entriesJohn Harrison
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi
2019-07-11drm/i915/tgl: Add vbt value mapping for DDC Bus pinMahesh Kumar
2019-07-11drm/i915/tgl: port to ddc pin mappingLucas De Marchi
2019-07-11drm/i915/tgl: Add gmbus gpio pin to port mappingMahesh Kumar
2019-07-11drm/i915/gen12: MBUS B credit changeRodrigo Vivi
2019-07-11drm/i915/tgl: apply Display WA #1178 to fix type C donglesLucas De Marchi
2019-07-11drm/i915/tgl: init ddi port A-C for Tiger LakeMahesh Kumar
2019-07-11drm/i915/tgl: Add additional PHYs for Tiger LakeLucas De Marchi
2019-07-11drm/i915/tgl: Add additional ports for Tiger LakeVandita Kulkarni
2019-07-11drm/i915/tgl: Add pll managerVandita Kulkarni
2019-07-11drm/i915/tgl: Add new pll idsVandita Kulkarni
2019-07-11drm/i915/tgl: Add power well to support 4th pipeMika Kahola
2019-07-11drm/i915/tgl: Add power well supportImre Deak
2019-07-11drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder AJosé Roberto de Souza
2019-07-11drm/i915/tgl: Check if pipe D is fusedJosé Roberto de Souza
2019-07-11drm/i915/tgl: Add TGL PCI IDsLucas De Marchi
2019-07-11drm/i915/tgl: Add TGL PCH detection in virtualized environmentMahesh Kumar
2019-07-11drm/i915/tgl: Introduce Tiger Lake PCHRadhakrishna Sripada
2019-07-11drm/i915/tgl: add initial Tiger Lake definitionsDaniele Ceraolo Spurio
2019-07-11drm/i915: Add 4th pipe and transcoderLucas De Marchi
2019-07-11drm/i915: Don't overestimate 4:2:0 link symbol clockVille Syrjälä
2019-07-11drm/i915: Copy name string into ring buffer for intel_update/disable_plane tr...Steven Rostedt (VMware)
2019-07-11drm/i915/guc: Drop redundant ctx param from kerneldocChris Wilson
2019-07-11drm/i915: Don't pass stack garbage to pcode in the second data registerVille Syrjälä
2019-07-11drm/i915: Use intel_ types in intel_atomic_commit()Ville Syrjälä
2019-07-11drm/i915: Use intel_ types in intel_{lock,modeset}_all_pipes()Ville Syrjälä
2019-07-11drm/i915: Polish intel_atomic_track_fbs()Ville Syrjälä
2019-07-11drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä
2019-07-11drm/i915: Simplify modeset_get_crtc_power_domains() argumentsVille Syrjälä
2019-07-11drm/i915: Check crtc_state->wm.need_postvbl_update before grabbing wm.mutexVille Syrjälä
2019-07-11drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()Ville Syrjälä
2019-07-11drm/i915/selftests: Hold the vma manager lock while modifying mmap_offsetChris Wilson
2019-07-11drm/i915/sdvo: Fix handling if zero hbuf sizeVille Syrjälä
2019-07-11drm/i915/guc: Simplify guc clientDaniele Ceraolo Spurio
2019-07-11drm/i915/guc: Remove preemption support for current fwChris Wilson
2019-07-11drm/i915/selftests: Ensure we don't clamp a random offset to 32bChris Wilson
2019-07-11drm/i915/gt: Drop the duplicate icl workaroundChris Wilson
2019-07-10drm/i915/ehl: Enable DDI-DMatt Roper
2019-07-10drm/i915: Transition port type checks to phy checksMatt Roper
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper
2019-07-10drm/i915/gen11: Start distinguishing 'phy' from 'port'Matt Roper
2019-07-10drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.cLucas De Marchi
2019-07-10drm/i915: fix include order in intel_tc.*Lucas De Marchi
2019-07-10drm/i915: make new intel_tc.c use uncore accessorsLucas De Marchi
2019-07-10Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi
2019-07-10drm/i915/icl: Fixed Input CSC Co-efficients for BT601/709Uma Shankar
2019-07-10drm/i915/icl: Fix Y pre-offset for Full Range YCbCrUma Shankar