diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_dma.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.h | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index fc5e3f41282d..035a709c7be1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -45,17 +45,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ #define NOUVEAU_DMA_SKIPS (128 / 4) -/* Hardcoded object assignments to subchannels (subchannel id). */ -enum { - NvSubCtxSurf2D = 0, - NvSubSw = 1, - NvSubImageBlit = 2, - NvSubGdiRect = 3, - - NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ - NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ -}; - /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, @@ -66,23 +55,6 @@ enum { NvEvoSema1 = 0x80000011, }; -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 -#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - static __must_check inline int RING_SPACE(struct nouveau_channel *chan, int size) { @@ -102,39 +74,6 @@ OUT_RING(struct nouveau_channel *chan, int data) nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); } -extern void -OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); - -static inline void -BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); -} - -static inline void -BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); -} - -static inline void -BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); -} - -static inline void -BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); -} - -static inline void -BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) -{ - OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); -} - #define WRITE_PUT(val) do { \ mb(); \ nouveau_bo_rd32(chan->push.buffer, 0); \ @@ -164,25 +103,6 @@ WIND_RING(struct nouveau_channel *chan) chan->dma.cur = chan->dma.put; } -/* FIFO methods */ -#define NV01_SUBCHAN_OBJECT 0x00000000 -#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 -#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 -#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 -#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 -#define NV84_SUBCHAN_UEVENT 0x00000020 -#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 -#define NV10_SUBCHAN_REF_CNT 0x00000050 -#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 -#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 -#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 -#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c -#define NV40_SUBCHAN_YIELD 0x00000080 - /* NV_SW object class */ #define NV_SW_DMA_VBLSEM 0x0000018c #define NV_SW_VBLSEM_OFFSET 0x00000400 |