diff options
Diffstat (limited to 'drivers/gpu/drm/etnaviv/state.xml.h')
| -rw-r--r-- | drivers/gpu/drm/etnaviv/state.xml.h | 103 |
1 files changed, 88 insertions, 15 deletions
diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h index 421cb7cc0053..573e39489a27 100644 --- a/drivers/gpu/drm/etnaviv/state.xml.h +++ b/drivers/gpu/drm/etnaviv/state.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26087 bytes, from 2017-12-18 16:51:59) -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54) -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) -- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) -- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) -- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) -- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) -- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) - -Copyright (C) 2012-2017 by the following authors: +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) + +Copyright (C) 2012-2024 by the following authors: - Wladimir J. van der Laan <laanwj@gmail.com> - Christian Gmeiner <christian.gmeiner@gmail.com> - Lucas Stach <l.stach@pengutronix.de> @@ -55,6 +55,8 @@ DEALINGS IN THE SOFTWARE. #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 #define FE_DATA_TYPE_INT 0x00000004 #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 +#define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006 +#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007 #define FE_DATA_TYPE_FLOAT 0x00000008 #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 #define FE_DATA_TYPE_FIXED 0x0000000b @@ -89,6 +91,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000 +#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16 @@ -209,7 +212,15 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) -#define VIVS_FE_HALTI5_UNK007C4 0x000007c4 +#define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK) +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK) #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 @@ -232,6 +243,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 +#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc + #define VIVS_GL 0x00000000 #define VIVS_GL_PIPE_SELECT 0x00003800 @@ -273,6 +286,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 +#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000 #define VIVS_GL_FLUSH_MMU 0x00003810 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 @@ -282,6 +296,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010 #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814 +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001 +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010 #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003 @@ -368,7 +384,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 -#define VIVS_GL_UNK03834 0x00003834 +#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834 #define VIVS_GL_UNK03838 0x00003838 @@ -387,7 +403,16 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c -#define VIVS_GL_HALTI5_UNK03884 0x00003884 +#define VIVS_GL_USC_CONTROL 0x00003884 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000 +#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16 +#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK) #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f @@ -421,7 +446,48 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_SECURITY_UNK3904 0x00003904 +#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK) + +#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0)) +#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004 +#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004 +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0 +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK) + +#define VIVS_GL_NN_CONFIG 0x00003930 +#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003 +#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0 +#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK) +#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004 +#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008 +#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK) +#define VIVS_GL_NN_CONFIG_UNK7 0x00000080 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK) +#define VIVS_GL_NN_CONFIG_UNK12 0x00001000 + +#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938 + +#define VIVS_GL_OCB_REMAP_START 0x0000393c + +#define VIVS_GL_OCB_REMAP_END 0x00003940 + +#define VIVS_GL_TP_CONFIG 0x0000394c + +#define VIVS_GL_UNK03950 0x00003950 + #define VIVS_GL_UNK03A00 0x00003a00 +#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007 +#define VIVS_GL_UNK03A00_UNK0__SHIFT 0 +#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK) #define VIVS_GL_UNK03A04 0x00003a04 @@ -451,7 +517,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) -#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) +#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0)) #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) @@ -498,5 +564,12 @@ DEALINGS IN THE SOFTWARE. #define VIVS_DUMMY_DUMMY 0x0003fffc +#define VIVS_WD 0x00000000 + +#define VIVS_WD_UNK18404 0x00018404 +#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003 +#define VIVS_WD_UNK18404_UNK0__SHIFT 0 +#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK) + #endif /* STATE_XML */ |