diff options
Diffstat (limited to 'drivers/clk/tegra/clk-tegra124.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 9a893f2fe8e9..11f857cd5f6a 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1014,6 +1014,9 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE }, { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, + { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA }, + { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X }, + { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI }, }; static struct clk **clks; @@ -1110,16 +1113,18 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; - clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0, + clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC, 30, 0, &pll_d_lock); - clks[TEGRA124_CLK_PLLD_DSI] = clk; + clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; - clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base, - 0, 48, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, + clk_base, 0, 48, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIA] = clk; - clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base, - 0, 82, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, + clk_base, 0, 82, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIB] = clk; /* emc mux */ @@ -1395,6 +1400,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { static struct tegra_clk_init_table tegra124_init_table[] __initdata = { {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1}, + {TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0}, + {TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0}, /* This MUST be the last entry. */ {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, }; @@ -1475,7 +1482,8 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) return; if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, - ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0) + ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq, + &pll_ref_freq) < 0) return; tegra_fixed_clk_init(tegra124_clks); |