summaryrefslogtreecommitdiff
path: root/arch/mips/pci
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile8
-rw-r--r--arch/mips/pci/fixup-capcella.c37
-rw-r--r--arch/mips/pci/fixup-jmr3927.c79
-rw-r--r--arch/mips/pci/fixup-lemote2f.c2
-rw-r--r--arch/mips/pci/fixup-mpc30x.c36
-rw-r--r--arch/mips/pci/fixup-sb1250.c2
-rw-r--r--arch/mips/pci/fixup-tb0219.c38
-rw-r--r--arch/mips/pci/fixup-tb0226.c73
-rw-r--r--arch/mips/pci/fixup-tb0287.c52
-rw-r--r--arch/mips/pci/msi-octeon.c16
-rw-r--r--arch/mips/pci/ops-tx3927.c231
-rw-r--r--arch/mips/pci/ops-vr41xx.c113
-rw-r--r--arch/mips/pci/pci-ar2315.c4
-rw-r--r--arch/mips/pci/pci-bcm63xx.c2
-rw-r--r--arch/mips/pci/pci-lantiq.c28
-rw-r--r--arch/mips/pci/pci-octeon.c2
-rw-r--r--arch/mips/pci/pci-vr41xx.c309
-rw-r--r--arch/mips/pci/pci-vr41xx.h141
-rw-r--r--arch/mips/pci/pcie-octeon.c4
19 files changed, 30 insertions, 1147 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 9a6bc702608c..a6e9785b537e 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -13,8 +13,6 @@ obj-$(CONFIG_PCI_DRIVERS_GENERIC)+= pci-generic.o
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
-obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
-obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
@@ -43,15 +41,9 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
-obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
-obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
-obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
-obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
-obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
-obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c
deleted file mode 100644
index dc8cd98a1761..000000000000
--- a/arch/mips/pci/fixup-capcella.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups.
- *
- * Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/vr41xx/capcella.h>
-
-/*
- * Shortcuts
- */
-#define INT1 RTL8139_1_IRQ
-#define INT2 RTL8139_2_IRQ
-#define INTA PC104PLUS_INTA_IRQ
-#define INTB PC104PLUS_INTB_IRQ
-#define INTC PC104PLUS_INTC_IRQ
-#define INTD PC104PLUS_INTD_IRQ
-
-static char irq_tab_capcella[][5] = {
- [11] = { -1, INT1, INT1, INT1, INT1 },
- [12] = { -1, INT2, INT2, INT2, INT2 },
- [14] = { -1, INTA, INTB, INTC, INTD }
-};
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- return irq_tab_capcella[slot][pin];
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c
deleted file mode 100644
index d3102eeea898..000000000000
--- a/arch/mips/pci/fixup-jmr3927.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Board specific pci fixups.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <asm/txx9/pci.h>
-#include <asm/txx9/jmr3927.h>
-
-int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- unsigned char irq = pin;
-
- /* IRQ rotation (PICMG) */
- irq--; /* 0-3 */
- if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
- /* PCI CardSlot (IDSEL=A23, DevNu=12) */
- /* PCIA => PCIC (IDSEL=A23) */
- /* NOTE: JMR3927 JP1 must be set to OPEN */
- irq = (irq + 2) % 4;
- } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
- /* PCI CardSlot (IDSEL=A22, DevNu=11) */
- /* PCIA => PCIA (IDSEL=A22) */
- /* NOTE: JMR3927 JP1 must be set to OPEN */
- irq = (irq + 0) % 4;
- } else {
- /* PCI Backplane */
- if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
- irq = (irq + 33 - slot) % 4;
- else
- irq = (irq + 3 + slot) % 4;
- }
- irq++; /* 1-4 */
-
- switch (irq) {
- case 1:
- irq = JMR3927_IRQ_IOC_PCIA;
- break;
- case 2:
- irq = JMR3927_IRQ_IOC_PCIB;
- break;
- case 3:
- irq = JMR3927_IRQ_IOC_PCIC;
- break;
- case 4:
- irq = JMR3927_IRQ_IOC_PCID;
- break;
- }
-
- /* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
- if (dev->bus->parent == NULL &&
- slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24))
- irq = JMR3927_IRQ_ETHER0;
- return irq;
-}
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 632ff2daa338..afafda03ed4e 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -80,7 +80,7 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
return dev->irq;
} else {
- printk(KERN_INFO " strange pci slot number.\n");
+ printk(KERN_INFO "strange PCI slot number.\n");
return 0;
}
}
diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c
deleted file mode 100644
index 27c75f268c4c..000000000000
--- a/arch/mips/pci/fixup-mpc30x.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * fixup-mpc30x.c, The Victor MP-C303/304 specific PCI fixups.
- *
- * Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/vr41xx/mpc30x.h>
-
-static const int internal_func_irqs[] = {
- VRC4173_CASCADE_IRQ,
- VRC4173_AC97_IRQ,
- VRC4173_USB_IRQ,
-};
-
-static const int irq_tab_mpc30x[] = {
- [12] = VRC4173_PCMCIA1_IRQ,
- [13] = VRC4173_PCMCIA2_IRQ,
- [29] = MQ200_IRQ,
-};
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if (slot == 30)
- return internal_func_irqs[PCI_FUNC(dev->devfn)];
-
- return irq_tab_mpc30x[slot];
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index 40efc990cdce..3f914c33b7de 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -75,7 +75,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
*/
static void quirk_sb1250_ht(struct pci_dev *dev)
{
- dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+ dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
quirk_sb1250_ht);
diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
deleted file mode 100644
index 43942998599b..000000000000
--- a/arch/mips/pci/fixup-tb0219.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
- *
- * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/vr41xx/tb0219.h>
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = -1;
-
- switch (slot) {
- case 12:
- irq = TB0219_PCI_SLOT1_IRQ;
- break;
- case 13:
- irq = TB0219_PCI_SLOT2_IRQ;
- break;
- case 14:
- irq = TB0219_PCI_SLOT3_IRQ;
- break;
- default:
- break;
- }
-
- return irq;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c
deleted file mode 100644
index a4d1efadfd4a..000000000000
--- a/arch/mips/pci/fixup-tb0226.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
- *
- * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/vr41xx/giu.h>
-#include <asm/vr41xx/tb0226.h>
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq = -1;
-
- switch (slot) {
- case 12:
- vr41xx_set_irq_trigger(GD82559_1_PIN,
- IRQ_TRIGGER_LEVEL,
- IRQ_SIGNAL_THROUGH);
- vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
- irq = GD82559_1_IRQ;
- break;
- case 13:
- vr41xx_set_irq_trigger(GD82559_2_PIN,
- IRQ_TRIGGER_LEVEL,
- IRQ_SIGNAL_THROUGH);
- vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
- irq = GD82559_2_IRQ;
- break;
- case 14:
- switch (pin) {
- case 1:
- vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
- IRQ_TRIGGER_LEVEL,
- IRQ_SIGNAL_THROUGH);
- vr41xx_set_irq_level(UPD720100_INTA_PIN,
- IRQ_LEVEL_LOW);
- irq = UPD720100_INTA_IRQ;
- break;
- case 2:
- vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
- IRQ_TRIGGER_LEVEL,
- IRQ_SIGNAL_THROUGH);
- vr41xx_set_irq_level(UPD720100_INTB_PIN,
- IRQ_LEVEL_LOW);
- irq = UPD720100_INTB_IRQ;
- break;
- case 3:
- vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
- IRQ_TRIGGER_LEVEL,
- IRQ_SIGNAL_THROUGH);
- vr41xx_set_irq_level(UPD720100_INTC_PIN,
- IRQ_LEVEL_LOW);
- irq = UPD720100_INTC_IRQ;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-
- return irq;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c
deleted file mode 100644
index 721ec9ac1c76..000000000000
--- a/arch/mips/pci/fixup-tb0287.c
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
- *
- * Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/vr41xx/tb0287.h>
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- unsigned char bus;
- int irq = -1;
-
- bus = dev->bus->number;
- if (bus == 0) {
- switch (slot) {
- case 16:
- irq = TB0287_SM501_IRQ;
- break;
- case 17:
- irq = TB0287_SIL680A_IRQ;
- break;
- default:
- break;
- }
- } else if (bus == 1) {
- switch (PCI_SLOT(dev->devfn)) {
- case 0:
- irq = TB0287_PCI_SLOT_IRQ;
- break;
- case 2:
- case 3:
- irq = TB0287_RTL8110_IRQ;
- break;
- default:
- break;
- }
- } else if (bus > 1) {
- irq = TB0287_PCI_SLOT_IRQ;
- }
-
- return irq;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index c2860ebbd863..abc3b61bff9f 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -46,16 +46,17 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
static int msi_irq_size;
/**
- * Called when a driver request MSI interrupts instead of the
+ * arch_setup_msi_irq() - setup MSI IRQs for a device
+ * @dev: Device requesting MSI interrupts
+ * @desc: MSI descriptor
+ *
+ * Called when a driver requests MSI interrupts instead of the
* legacy INT A-D. This routine will allocate multiple interrupts
* for MSI devices that support them. A device can override this by
* programming the MSI control bits [6:4] before calling
* pci_enable_msi().
*
- * @dev: Device requesting MSI interrupts
- * @desc: MSI descriptor
- *
- * Returns 0 on success.
+ * Return: %0 on success, non-%0 on error.
*/
int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
{
@@ -186,10 +187,11 @@ msi_irq_allocated:
}
/**
+ * arch_teardown_msi_irq() - release MSI IRQs for a device
+ * @irq: The devices first irq number. There may be multiple in sequence.
+ *
* Called when a device no longer needs its MSI interrupts. All
* MSI interrupts for the device are freed.
- *
- * @irq: The devices first irq number. There may be multple in sequence.
*/
void arch_teardown_msi_irq(unsigned int irq)
{
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
deleted file mode 100644
index d35dc9c9ab9d..000000000000
--- a/arch/mips/pci/ops-tx3927.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ahennessy@mvista.com
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
- *
- * Define the pci_ops for TX3927.
- *
- * Much of the code is derived from the original DDB5074 port by
- * Geert Uytterhoeven <geert@linux-m68k.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#include <asm/addrspace.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/pci.h>
-#include <asm/txx9/tx3927.h>
-
-static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
-{
- if (bus->parent == NULL &&
- devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
- return -1;
- tx3927_pcicptr->ica =
- ((bus->number & 0xff) << 0x10) |
- ((devfn & 0xff) << 0x08) |
- (where & 0xfc) | (bus->parent ? 1 : 0);
-
- /* clear M_ABORT and Disable M_ABORT Int. */
- tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
- tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
- return 0;
-}
-
-static inline int check_abort(void)
-{
- if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
- tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
- tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
- /* flush write buffer */
- iob();
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 * val)
-{
- if (mkaddr(bus, devfn, where)) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- switch (size) {
- case 1:
- *val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
- break;
-
- case 2:
- *val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
- break;
-
- case 4:
- *val = le32_to_cpu(tx3927_pcicptr->icd);
- break;
- }
-
- return check_abort();
-}
-
-static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- if (mkaddr(bus, devfn, where))
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- switch (size) {
- case 1:
- *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
- break;
-
- case 2:
- *(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
- cpu_to_le16(val);
- break;
-
- case 4:
- tx3927_pcicptr->icd = cpu_to_le32(val);
- }
-
- return check_abort();
-}
-
-static struct pci_ops tx3927_pci_ops = {
- .read = tx3927_pci_read_config,
- .write = tx3927_pci_write_config,
-};
-
-void __init tx3927_pcic_setup(struct pci_controller *channel,
- unsigned long sdram_size, int extarb)
-{
- unsigned long flags;
- unsigned long io_base =
- channel->io_resource->start + mips_io_port_base - IO_BASE;
- unsigned long io_size =
- channel->io_resource->end - channel->io_resource->start;
- unsigned long io_pciaddr =
- channel->io_resource->start - channel->io_offset;
- unsigned long mem_base =
- channel->mem_resource->start;
- unsigned long mem_size =
- channel->mem_resource->end - channel->mem_resource->start;
- unsigned long mem_pciaddr =
- channel->mem_resource->start - channel->mem_offset;
-
- printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
- tx3927_pcicptr->did, tx3927_pcicptr->vid,
- tx3927_pcicptr->rid,
- extarb ? "External" : "Internal");
- channel->pci_ops = &tx3927_pci_ops;
-
- local_irq_save(flags);
- /* Disable External PCI Config. Access */
- tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
-#ifdef __BIG_ENDIAN
- tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
- TX3927_PCIC_LBC_TIBSE |
- TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
-#endif
- /* LB->PCI mappings */
- tx3927_pcicptr->iomas = ~(io_size - 1);
- tx3927_pcicptr->ilbioma = io_base;
- tx3927_pcicptr->ipbioma = io_pciaddr;
- tx3927_pcicptr->mmas = ~(mem_size - 1);
- tx3927_pcicptr->ilbmma = mem_base;
- tx3927_pcicptr->ipbmma = mem_pciaddr;
- /* PCI->LB mappings */
- tx3927_pcicptr->iobas = 0xffffffff;
- tx3927_pcicptr->ioba = 0;
- tx3927_pcicptr->tlbioma = 0;
- tx3927_pcicptr->mbas = ~(sdram_size - 1);
- tx3927_pcicptr->mba = 0;
- tx3927_pcicptr->tlbmma = 0;
- /* Enable Direct mapping Address Space Decoder */
- tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
-
- /* Clear All Local Bus Status */
- tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
- /* Enable All Local Bus Interrupts */
- tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
- /* Clear All PCI Status Error */
- tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
- /* Enable All PCI Status Error Interrupts */
- tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
-
- /* PCIC Int => IRC IRQ10 */
- tx3927_pcicptr->il = TX3927_IR_PCI;
- /* Target Control (per errata) */
- tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
-
- /* Enable Bus Arbiter */
- if (!extarb)
- tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
-
- tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_IO |
- PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
- local_irq_restore(flags);
-}
-
-static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id)
-{
- struct pt_regs *regs = get_irq_regs();
-
- if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
- printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n",
- regs->cp0_epc);
- printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
- tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
- }
- if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
- /* clear all pci errors */
- tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL;
- tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL;
- tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL;
- tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
- return IRQ_HANDLED;
- }
- console_verbose();
- panic("PCI error.");
-}
-
-void __init tx3927_setup_pcierr_irq(void)
-{
- if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
- tx3927_pcierr_interrupt,
- 0, "PCI error",
- (void *)TX3927_PCIC_REG))
- printk(KERN_WARNING "Failed to request irq for PCIERR\n");
-}
diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c
deleted file mode 100644
index 7b7709aa14c7..000000000000
--- a/arch/mips/pci/ops-vr41xx.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
- *
- * Copyright (C) 2001-2003 MontaVista Software Inc.
- * Author: Yoichi Yuasa <source@mvista.com>
- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-/*
- * Changes:
- * MontaVista Software Inc. <source@mvista.com>
- * - New creation, NEC VR4122 and VR4131 are supported.
- */
-#include <linux/pci.h>
-#include <linux/types.h>
-
-#include <asm/io.h>
-
-#define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
-#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
-
-static inline int set_pci_configuration_address(unsigned char number,
- unsigned int devfn, int where)
-{
- if (number == 0) {
- /*
- * Type 0 configuration
- */
- if (PCI_SLOT(devfn) < 11 || where > 0xff)
- return -EINVAL;
-
- writel((1U << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
- (where & 0xfc), PCICONFAREG);
- } else {
- /*
- * Type 1 configuration
- */
- if (where > 0xff)
- return -EINVAL;
-
- writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) |
- (where & 0xfc) | 1U, PCICONFAREG);
- }
-
- return 0;
-}
-
-static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *val)
-{
- uint32_t data;
-
- *val = 0xffffffffU;
- if (set_pci_configuration_address(bus->number, devfn, where) < 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- data = readl(PCICONFDREG);
-
- switch (size) {
- case 1:
- *val = (data >> ((where & 3) << 3)) & 0xffU;
- break;
- case 2:
- *val = (data >> ((where & 2) << 3)) & 0xffffU;
- break;
- case 4:
- *val = data;
- break;
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t val)
-{
- uint32_t data;
- int shift;
-
- if (set_pci_configuration_address(bus->number, devfn, where) < 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- data = readl(PCICONFDREG);
-
- switch (size) {
- case 1:
- shift = (where & 3) << 3;
- data &= ~(0xffU << shift);
- data |= ((val & 0xffU) << shift);
- break;
- case 2:
- shift = (where & 2) << 3;
- data &= ~(0xffffU << shift);
- data |= ((val & 0xffffU) << shift);
- break;
- case 4:
- data = val;
- break;
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
-
- writel(data, PCICONFDREG);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops vr41xx_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c
index 9a4bfb4e63e3..e17d862cfa4c 100644
--- a/arch/mips/pci/pci-ar2315.c
+++ b/arch/mips/pci/pci-ar2315.c
@@ -2,7 +2,7 @@
/*
*/
-/**
+/*
* Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
* and interrupt. PCI interface supports MMIO access method, but does not
* seem to support I/O ports.
@@ -384,7 +384,7 @@ static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
return 0;
}
-static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
+static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
.map = ar2315_pci_irq_map,
};
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 5548365605c0..ac83243772d2 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -186,7 +186,7 @@ static int __init bcm63xx_register_pcie(void)
/* setup class code as bridge */
val = bcm_pcie_readl(PCIE_IDVAL3_REG);
val &= ~IDVAL3_CLASS_CODE_MASK;
- val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+ val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
bcm_pcie_writel(val, PCIE_IDVAL3_REG);
/* disable bar1 size */
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 1ca42f482130..8d16cd021f60 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -9,11 +9,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/clk.h>
#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
@@ -62,7 +62,7 @@
__iomem void *ltq_pci_mapped_cfg;
static __iomem void *ltq_pci_membase;
-static int reset_gpio;
+static struct gpio_desc *reset_gpio;
static struct clk *clk_pci, *clk_external;
static struct resource pci_io_resource;
static struct resource pci_mem_resource;
@@ -95,6 +95,7 @@ static int ltq_pci_startup(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
const __be32 *req_mask, *bus_clk;
u32 temp_buffer;
+ int error;
/* get our clocks */
clk_pci = clk_get(&pdev->dev, NULL);
@@ -123,17 +124,14 @@ static int ltq_pci_startup(struct platform_device *pdev)
clk_disable(clk_external);
/* setup reset gpio used by pci */
- reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
- if (gpio_is_valid(reset_gpio)) {
- int ret = devm_gpio_request(&pdev->dev,
- reset_gpio, "pci-reset");
- if (ret) {
- dev_err(&pdev->dev,
- "failed to request gpio %d\n", reset_gpio);
- return ret;
- }
- gpio_direction_output(reset_gpio, 1);
+ reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+ GPIOD_OUT_LOW);
+ error = PTR_ERR_OR_ZERO(reset_gpio);
+ if (error) {
+ dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
+ return error;
}
+ gpiod_set_consumer_name(reset_gpio, "pci_reset");
/* enable auto-switching between PCI and EBU */
ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
@@ -195,11 +193,11 @@ static int ltq_pci_startup(struct platform_device *pdev)
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
/* toggle reset pin */
- if (gpio_is_valid(reset_gpio)) {
- __gpio_set_value(reset_gpio, 0);
+ if (reset_gpio) {
+ gpiod_set_value_cansleep(reset_gpio, 1);
wmb();
mdelay(1);
- __gpio_set_value(reset_gpio, 1);
+ gpiod_set_value_cansleep(reset_gpio, 0);
}
return 0;
}
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index fc29b85cfa92..e457a18cbdc5 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -664,7 +664,7 @@ static int __init octeon_pci_setup(void)
/* BAR1 movable regions contiguous to cover the swiotlb */
octeon_bar1_pci_phys =
- virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
+ io_tlb_default_mem.start & ~((1ull << 22) - 1);
for (index = 0; index < 32; index++) {
union cvmx_pci_bar1_indexx bar1_index;
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
deleted file mode 100644
index 4f250c55b6e6..000000000000
--- a/arch/mips/pci/pci-vr41xx.c
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
- *
- * Copyright (C) 2001-2003 MontaVista Software Inc.
- * Author: Yoichi Yuasa <source@mvista.com>
- * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- */
-/*
- * Changes:
- * MontaVista Software Inc. <source@mvista.com>
- * - New creation, NEC VR4122 and VR4131 are supported.
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/types.h>
-
-#include <asm/cpu.h>
-#include <asm/io.h>
-#include <asm/vr41xx/pci.h>
-#include <asm/vr41xx/vr41xx.h>
-
-#include "pci-vr41xx.h"
-
-extern struct pci_ops vr41xx_pci_ops;
-
-static void __iomem *pciu_base;
-
-#define pciu_read(offset) readl(pciu_base + (offset))
-#define pciu_write(offset, value) writel((value), pciu_base + (offset))
-
-static struct pci_master_address_conversion pci_master_memory1 = {
- .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
- .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK,
- .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
-};
-
-static struct pci_target_address_conversion pci_target_memory1 = {
- .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK,
- .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS,
-};
-
-static struct pci_master_address_conversion pci_master_io = {
- .bus_base_address = PCI_MASTER_IO_BUS_BASE_ADDRESS,
- .address_mask = PCI_MASTER_IO_ADDRESS_MASK,
- .pci_base_address = PCI_MASTER_IO_PCI_BASE_ADDRESS,
-};
-
-static struct pci_mailbox_address pci_mailbox = {
- .base_address = PCI_MAILBOX_BASE_ADDRESS,
-};
-
-static struct pci_target_address_window pci_target_window1 = {
- .base_address = PCI_TARGET_WINDOW1_BASE_ADDRESS,
-};
-
-static struct resource pci_mem_resource = {
- .name = "PCI Memory resources",
- .start = PCI_MEM_RESOURCE_START,
- .end = PCI_MEM_RESOURCE_END,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource pci_io_resource = {
- .name = "PCI I/O resources",
- .start = PCI_IO_RESOURCE_START,
- .end = PCI_IO_RESOURCE_END,
- .flags = IORESOURCE_IO,
-};
-
-static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
- .master_memory1 = &pci_master_memory1,
- .target_memory1 = &pci_target_memory1,
- .master_io = &pci_master_io,
- .exclusive_access = CANNOT_LOCK_FROM_DEVICE,
- .wait_time_limit_from_irdy_to_trdy = 0,
- .mailbox = &pci_mailbox,
- .target_window1 = &pci_target_window1,
- .master_latency_timer = 0x80,
- .retry_limit = 0,
- .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR,
- .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE,
-};
-
-static struct pci_controller vr41xx_pci_controller = {
- .pci_ops = &vr41xx_pci_ops,
- .mem_resource = &pci_mem_resource,
- .io_resource = &pci_io_resource,
-};
-
-void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup)
-{
- vr41xx_pci_controller_unit_setup = *setup;
-}
-
-static int __init vr41xx_pciu_init(void)
-{
- struct pci_controller_unit_setup *setup;
- struct pci_master_address_conversion *master;
- struct pci_target_address_conversion *target;
- struct pci_mailbox_address *mailbox;
- struct pci_target_address_window *window;
- unsigned long vtclock, pci_clock_max;
- uint32_t val;
-
- setup = &vr41xx_pci_controller_unit_setup;
-
- if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
- return -EBUSY;
-
- pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
- if (pciu_base == NULL) {
- release_mem_region(PCIU_BASE, PCIU_SIZE);
- return -EBUSY;
- }
-
- /* Disable PCI interrupt */
- vr41xx_disable_pciint();
-
- /* Supply VTClock to PCIU */
- vr41xx_supply_clock(PCIU_CLOCK);
-
- /* Dummy write, waiting for supply of VTClock. */
- vr41xx_disable_pciint();
-
- /* Select PCI clock */
- if (setup->pci_clock_max != 0)
- pci_clock_max = setup->pci_clock_max;
- else
- pci_clock_max = PCI_CLOCK_MAX;
- vtclock = vr41xx_get_vtclock_frequency();
- if (vtclock < pci_clock_max)
- pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
- else if ((vtclock / 2) < pci_clock_max)
- pciu_write(PCICLKSELREG, HALF_VTCLOCK);
- else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
- (vtclock / 3) < pci_clock_max)
- pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
- else if ((vtclock / 4) < pci_clock_max)
- pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
- else {
- printk(KERN_ERR "PCI Clock is over 33MHz.\n");
- iounmap(pciu_base);
- return -EINVAL;
- }
-
- /* Supply PCI clock by PCI bus */
- vr41xx_supply_clock(PCI_CLOCK);
-
- if (setup->master_memory1 != NULL) {
- master = setup->master_memory1;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIA(master->pci_base_address);
- pciu_write(PCIMMAW1REG, val);
- } else {
- val = pciu_read(PCIMMAW1REG);
- val &= ~WINEN;
- pciu_write(PCIMMAW1REG, val);
- }
-
- if (setup->master_memory2 != NULL) {
- master = setup->master_memory2;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIA(master->pci_base_address);
- pciu_write(PCIMMAW2REG, val);
- } else {
- val = pciu_read(PCIMMAW2REG);
- val &= ~WINEN;
- pciu_write(PCIMMAW2REG, val);
- }
-
- if (setup->target_memory1 != NULL) {
- target = setup->target_memory1;
- val = TARGET_MSK(target->address_mask) |
- WINEN |
- ITA(target->bus_base_address);
- pciu_write(PCITAW1REG, val);
- } else {
- val = pciu_read(PCITAW1REG);
- val &= ~WINEN;
- pciu_write(PCITAW1REG, val);
- }
-
- if (setup->target_memory2 != NULL) {
- target = setup->target_memory2;
- val = TARGET_MSK(target->address_mask) |
- WINEN |
- ITA(target->bus_base_address);
- pciu_write(PCITAW2REG, val);
- } else {
- val = pciu_read(PCITAW2REG);
- val &= ~WINEN;
- pciu_write(PCITAW2REG, val);
- }
-
- if (setup->master_io != NULL) {
- master = setup->master_io;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIIA(master->pci_base_address);
- pciu_write(PCIMIOAWREG, val);
- } else {
- val = pciu_read(PCIMIOAWREG);
- val &= ~WINEN;
- pciu_write(PCIMIOAWREG, val);
- }
-
- if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
- pciu_write(PCIEXACCREG, UNLOCK);
- else
- pciu_write(PCIEXACCREG, 0);
-
- if (current_cpu_type() == CPU_VR4122)
- pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
-
- pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
-
- if (setup->mailbox != NULL) {
- mailbox = setup->mailbox;
- val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
- MSI_MEMORY | PREF_APPROVAL;
- pciu_write(MAILBAREG, val);
- }
-
- if (setup->target_window1) {
- window = setup->target_window1;
- val = PMBA(window->base_address) | TYPE_32BITSPACE |
- MSI_MEMORY | PREF_APPROVAL;
- pciu_write(PCIMBA1REG, val);
- }
-
- if (setup->target_window2) {
- window = setup->target_window2;
- val = PMBA(window->base_address) | TYPE_32BITSPACE |
- MSI_MEMORY | PREF_APPROVAL;
- pciu_write(PCIMBA2REG, val);
- }
-
- val = pciu_read(RETVALREG);
- val &= ~RTYVAL_MASK;
- val |= RTYVAL(setup->retry_limit);
- pciu_write(RETVALREG, val);
-
- val = pciu_read(PCIAPCNTREG);
- val &= ~(TKYGNT | PAPC);
-
- switch (setup->arbiter_priority_control) {
- case PCI_ARBITRATION_MODE_ALTERNATE_0:
- val |= PAPC_ALTERNATE_0;
- break;
- case PCI_ARBITRATION_MODE_ALTERNATE_B:
- val |= PAPC_ALTERNATE_B;
- break;
- default:
- val |= PAPC_FAIR;
- break;
- }
-
- if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
- val |= TKYGNT_ENABLE;
-
- pciu_write(PCIAPCNTREG, val);
-
- pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
- PCI_COMMAND_SERR);
-
- /* Clear bus error */
- pciu_read(BUSERRADREG);
-
- pciu_write(PCIENREG, PCIU_CONFIG_DONE);
-
- if (setup->mem_resource != NULL)
- vr41xx_pci_controller.mem_resource = setup->mem_resource;
-
- if (setup->io_resource != NULL) {
- vr41xx_pci_controller.io_resource = setup->io_resource;
- } else {
- set_io_port_base(IO_PORT_BASE);
- ioport_resource.start = IO_PORT_RESOURCE_START;
- ioport_resource.end = IO_PORT_RESOURCE_END;
- }
-
- if (setup->master_io) {
- void __iomem *io_map_base;
- struct resource *res = vr41xx_pci_controller.io_resource;
- master = setup->master_io;
- io_map_base = ioremap(master->bus_base_address,
- resource_size(res));
- if (!io_map_base) {
- iounmap(pciu_base);
- return -EBUSY;
- }
-
- vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base;
- }
-
- register_pci_controller(&vr41xx_pci_controller);
-
- return 0;
-}
-
-arch_initcall(vr41xx_pciu_init);
diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h
deleted file mode 100644
index 5595e4a39b2a..000000000000
--- a/arch/mips/pci/pci-vr41xx.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
- *
- * Copyright (C) 2002 MontaVista Software Inc.
- * Author: Yoichi Yuasa <source@mvista.com>
- * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
- */
-#ifndef __PCI_VR41XX_H
-#define __PCI_VR41XX_H
-
-#define PCIU_BASE 0x0f000c00UL
-#define PCIU_SIZE 0x200UL
-
-#define PCIMMAW1REG 0x00
-#define PCIMMAW2REG 0x04
-#define PCITAW1REG 0x08
-#define PCITAW2REG 0x0c
-#define PCIMIOAWREG 0x10
- #define IBA(addr) ((addr) & 0xff000000U)
- #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
- #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
- #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U)
- #define ITA(addr) (((addr) >> 24) & 0x000000ffU)
- #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
- #define WINEN 0x1000U
-#define PCICONFDREG 0x14
-#define PCICONFAREG 0x18
-#define PCIMAILREG 0x1c
-#define BUSERRADREG 0x24
- #define EA(reg) ((reg) &0xfffffffc)
-
-#define INTCNTSTAREG 0x28
- #define MABTCLR 0x80000000U
- #define TRDYCLR 0x40000000U
- #define PARCLR 0x20000000U
- #define MBCLR 0x10000000U
- #define SERRCLR 0x08000000U
- #define RTYCLR 0x04000000U
- #define MABCLR 0x02000000U
- #define TABCLR 0x01000000U
- /* RFU */
- #define MABTMSK 0x00008000U
- #define TRDYMSK 0x00004000U
- #define PARMSK 0x00002000U
- #define MBMSK 0x00001000U
- #define SERRMSK 0x00000800U
- #define RTYMSK 0x00000400U
- #define MABMSK 0x00000200U
- #define TABMSK 0x00000100U
- #define IBAMABT 0x00000080U
- #define TRDYRCH 0x00000040U
- #define PAR 0x00000020U
- #define MB 0x00000010U
- #define PCISERR 0x00000008U
- #define RTYRCH 0x00000004U
- #define MABORT 0x00000002U
- #define TABORT 0x00000001U
-
-#define PCIEXACCREG 0x2c
- #define UNLOCK 0x2U
- #define EAREQ 0x1U
-#define PCIRECONTREG 0x30
- #define RTRYCNT(reg) ((reg) & 0x000000ffU)
-#define PCIENREG 0x34
- #define PCIU_CONFIG_DONE 0x4U
-#define PCICLKSELREG 0x38
- #define EQUAL_VTCLOCK 0x2U
- #define HALF_VTCLOCK 0x0U
- #define ONE_THIRD_VTCLOCK 0x3U
- #define QUARTER_VTCLOCK 0x1U
-#define PCITRDYVREG 0x3c
- #define TRDYV(val) ((uint32_t)(val) & 0xffU)
-#define PCICLKRUNREG 0x60
-
-#define VENDORIDREG 0x100
-#define DEVICEIDREG 0x100
-#define COMMANDREG 0x104
-#define STATUSREG 0x104
-#define REVIDREG 0x108
-#define CLASSREG 0x108
-#define CACHELSREG 0x10c
-#define LATTIMEREG 0x10c
- #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
-#define MAILBAREG 0x110
-#define PCIMBA1REG 0x114
-#define PCIMBA2REG 0x118
- #define MBADD(base) ((base) & 0xfffff800U)
- #define PMBA(base) ((base) & 0xffe00000U)
- #define PREF 0x8U
- #define PREF_APPROVAL 0x8U
- #define PREF_DISAPPROVAL 0x0U
- #define TYPE 0x6U
- #define TYPE_32BITSPACE 0x0U
- #define MSI 0x1U
- #define MSI_MEMORY 0x0U
-#define INTLINEREG 0x13c
-#define INTPINREG 0x13c
-#define RETVALREG 0x140
-#define PCIAPCNTREG 0x140
- #define TKYGNT 0x04000000U
- #define TKYGNT_ENABLE 0x04000000U
- #define TKYGNT_DISABLE 0x00000000U
- #define PAPC 0x03000000U
- #define PAPC_ALTERNATE_B 0x02000000U
- #define PAPC_ALTERNATE_0 0x01000000U
- #define PAPC_FAIR 0x00000000U
- #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U)
- #define RTYVAL_MASK 0xff00U
-
-#define PCI_CLOCK_MAX 33333333U
-
-/*
- * Default setup
- */
-#define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U
-#define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U
-#define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U
-
-#define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U
-#define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U
-
-#define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U
-#define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U
-#define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U
-
-#define PCI_MAILBOX_BASE_ADDRESS 0x00000000U
-
-#define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U
-
-#define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
-#define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS
-#define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
-
-#define PCI_IO_RESOURCE_START 0x01000000UL
-#define PCI_IO_RESOURCE_END 0x01ffffffUL
-
-#define PCI_MEM_RESOURCE_START 0x11000000UL
-#define PCI_MEM_RESOURCE_END 0x13ffffffUL
-
-#endif /* __PCI_VR41XX_H */
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index d919a0d813a1..c9edd3fb380d 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -895,7 +895,7 @@ retry:
mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
- mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
+ mem_access_subid.s.ba = 0; /* PCIe Address Bits <63:34>. */
/*
* Setup mem access 12-15 for port 0, 16-19 for port 1,
@@ -1345,7 +1345,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
- /* PCIe Adddress Bits <63:34>. */
+ /* PCIe Address Bits <63:34>. */
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
mem_access_subid.cn68xx.ba = 0;
else