diff options
Diffstat (limited to 'arch/arm/mach-s5p6442')
23 files changed, 1410 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig new file mode 100644 index 000000000000..4f3f6de6a013 --- /dev/null +++ b/arch/arm/mach-s5p6442/Kconfig @@ -0,0 +1,24 @@ +# arch/arm/mach-s5p6442/Kconfig +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +# Configuration options for the S5P6442 + +if ARCH_S5P6442 + +config CPU_S5P6442 + bool + select PLAT_S5P + help + Enable S5P6442 CPU support + +config MACH_SMDK6442 + bool "SMDK6442" + select CPU_S5P6442 + help + Machine support for Samsung SMDK6442 + +endif diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile new file mode 100644 index 000000000000..dde39a6ce6bc --- /dev/null +++ b/arch/arm/mach-s5p6442/Makefile @@ -0,0 +1,19 @@ +# arch/arm/mach-s5p6442/Makefile +# +# Copyright (c) 2010 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S5P6442 system + +obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o + +# machine support + +obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o diff --git a/arch/arm/mach-s5p6442/Makefile.boot b/arch/arm/mach-s5p6442/Makefile.boot new file mode 100644 index 000000000000..ff90aa13bd67 --- /dev/null +++ b/arch/arm/mach-s5p6442/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c new file mode 100644 index 000000000000..3aadbf42c112 --- /dev/null +++ b/arch/arm/mach-s5p6442/clock.c @@ -0,0 +1,396 @@ +/* linux/arch/arm/mach-s5p6442/clock.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/cpu-freq.h> +#include <mach/regs-clock.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/pll.h> +#include <plat/s5p-clock.h> +#include <plat/clock-clksrc.h> +#include <plat/s5p6442.h> + +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, +}; + +/* Possible clock sources for ARM Mux */ +static struct clk *clk_src_arm_list[] = { + [1] = &clk_mout_apll.clk, + [2] = &clk_mout_mpll.clk, +}; + +static struct clksrc_sources clk_src_arm = { + .sources = clk_src_arm_list, + .nr_sources = ARRAY_SIZE(clk_src_arm_list), +}; + +static struct clksrc_clk clk_mout_arm = { + .clk = { + .name = "mout_arm", + .id = -1, + }, + .sources = &clk_src_arm, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, +}; + +static struct clk clk_dout_a2m = { + .name = "dout_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, +}; + +/* Possible clock sources for D0 Mux */ +static struct clk *clk_src_d0_list[] = { + [1] = &clk_mout_mpll.clk, + [2] = &clk_dout_a2m, +}; + +static struct clksrc_sources clk_src_d0 = { + .sources = clk_src_d0_list, + .nr_sources = ARRAY_SIZE(clk_src_d0_list), +}; + +static struct clksrc_clk clk_mout_d0 = { + .clk = { + .name = "mout_d0", + .id = -1, + }, + .sources = &clk_src_d0, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 }, +}; + +static struct clk clk_dout_apll = { + .name = "dout_apll", + .id = -1, + .parent = &clk_mout_arm.clk, +}; + +/* Possible clock sources for D0SYNC Mux */ +static struct clk *clk_src_d0sync_list[] = { + [1] = &clk_mout_d0.clk, + [2] = &clk_dout_apll, +}; + +static struct clksrc_sources clk_src_d0sync = { + .sources = clk_src_d0sync_list, + .nr_sources = ARRAY_SIZE(clk_src_d0sync_list), +}; + +static struct clksrc_clk clk_mout_d0sync = { + .clk = { + .name = "mout_d0sync", + .id = -1, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, +}; + +/* Possible clock sources for D1 Mux */ +static struct clk *clk_src_d1_list[] = { + [1] = &clk_mout_mpll.clk, + [2] = &clk_dout_a2m, +}; + +static struct clksrc_sources clk_src_d1 = { + .sources = clk_src_d1_list, + .nr_sources = ARRAY_SIZE(clk_src_d1_list), +}; + +static struct clksrc_clk clk_mout_d1 = { + .clk = { + .name = "mout_d1", + .id = -1, + }, + .sources = &clk_src_d1, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 }, +}; + +/* Possible clock sources for D1SYNC Mux */ +static struct clk *clk_src_d1sync_list[] = { + [1] = &clk_mout_d1.clk, + [2] = &clk_dout_apll, +}; + +static struct clksrc_sources clk_src_d1sync = { + .sources = clk_src_d1sync_list, + .nr_sources = ARRAY_SIZE(clk_src_d1sync_list), +}; + +static struct clksrc_clk clk_mout_d1sync = { + .clk = { + .name = "mout_d1sync", + .id = -1, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, +}; + +static struct clk clk_hclkd0 = { + .name = "hclkd0", + .id = -1, + .parent = &clk_mout_d0sync.clk, +}; + +static struct clk clk_hclkd1 = { + .name = "hclkd1", + .id = -1, + .parent = &clk_mout_d1sync.clk, +}; + +static struct clk clk_pclkd0 = { + .name = "pclkd0", + .id = -1, + .parent = &clk_hclkd0, +}; + +static struct clk clk_pclkd1 = { + .name = "pclkd1", + .id = -1, + .parent = &clk_hclkd1, +}; + +int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); +} + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "dout_a2m", + .id = -1, + .parent = &clk_mout_apll.clk, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, + }, { + .clk = { + .name = "dout_apll", + .id = -1, + .parent = &clk_mout_arm.clk, + }, + .sources = &clk_src_arm, + .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, + }, { + .clk = { + .name = "hclkd1", + .id = -1, + .parent = &clk_mout_d1sync.clk, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "hclkd0", + .id = -1, + .parent = &clk_mout_d0sync.clk, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "pclkd0", + .id = -1, + .parent = &clk_hclkd0, + }, + .sources = &clk_src_d0sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, + }, { + .clk = { + .name = "pclkd1", + .id = -1, + .parent = &clk_hclkd1, + }, + .sources = &clk_src_d1sync, + .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, + } +}; + +/* Clock initialisation code */ +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_mpll, + &clk_mout_epll, + &clk_mout_arm, + &clk_mout_d0, + &clk_mout_d0sync, + &clk_mout_d1, + &clk_mout_d1sync, +}; + +void __init_or_cpufreq s5p6442_setup_clocks(void) +{ + struct clk *pclkd0_clk; + struct clk *pclkd1_clk; + + unsigned long xtal; + unsigned long arm; + unsigned long hclkd0 = 0; + unsigned long hclkd1 = 0; + unsigned long pclkd0 = 0; + unsigned long pclkd1 = 0; + + unsigned long apll; + unsigned long mpll; + unsigned long epll; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal = clk_get_rate(&clk_xtal); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); + epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); + + printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", + apll, mpll, epll); + + clk_fout_apll.rate = apll; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); + + arm = clk_get_rate(&clk_dout_apll); + hclkd0 = clk_get_rate(&clk_hclkd0); + hclkd1 = clk_get_rate(&clk_hclkd1); + + pclkd0_clk = clk_get(NULL, "pclkd0"); + BUG_ON(IS_ERR(pclkd0_clk)); + + pclkd0 = clk_get_rate(pclkd0_clk); + clk_put(pclkd0_clk); + + pclkd1_clk = clk_get(NULL, "pclkd1"); + BUG_ON(IS_ERR(pclkd1_clk)); + + pclkd1 = clk_get_rate(pclkd1_clk); + clk_put(pclkd1_clk); + + printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n", + hclkd0, hclkd1, pclkd0, pclkd1); + + /* For backward compatibility */ + clk_f.rate = arm; + clk_h.rate = hclkd1; + clk_p.rate = pclkd1; + + clk_pclkd0.rate = pclkd0; + clk_pclkd1.rate = pclkd1; +} + +static struct clk init_clocks[] = { + { + .name = "systimer", + .id = -1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<16), + }, { + .name = "uart", + .id = 0, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<17), + }, { + .name = "uart", + .id = 1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<18), + }, { + .name = "uart", + .id = 2, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<19), + }, { + .name = "timers", + .id = -1, + .parent = &clk_pclkd1, + .enable = s5p6442_clk_ip3_ctrl, + .ctrlbit = (1<<23), + }, +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_mout_apll.clk, + &clk_mout_mpll.clk, + &clk_mout_epll.clk, + &clk_mout_d0.clk, + &clk_mout_d0sync.clk, + &clk_mout_d1.clk, + &clk_mout_d1sync.clk, + &clk_hclkd0, + &clk_pclkd0, + &clk_hclkd1, + &clk_pclkd1, +}; + +void __init s5p6442_register_clocks(void) +{ + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + s3c_pwmclk_init(); +} diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c new file mode 100644 index 000000000000..bc2524df89b3 --- /dev/null +++ b/arch/arm/mach-s5p6442/cpu.c @@ -0,0 +1,121 @@ +/* linux/arch/arm/mach-s5p6442/cpu.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/sysdev.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/proc-fns.h> + +#include <mach/hardware.h> +#include <mach/map.h> +#include <asm/irq.h> + +#include <plat/regs-serial.h> +#include <mach/regs-clock.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> +#include <plat/s5p6442.h> + +/* Initial IO mappings */ + +static struct map_desc s5p6442_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC2, + .pfn = __phys_to_pfn(S5P6442_PA_VIC2), + .length = SZ_16K, + .type = MT_DEVICE, + } +}; + +static void s5p6442_idle(void) +{ + if (!need_resched()) + cpu_do_idle(); + + local_irq_enable(); +} + +/* s5p6442_map_io + * + * register the standard cpu IO areas +*/ + +void __init s5p6442_map_io(void) +{ + iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc)); +} + +void __init s5p6442_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5p6442_register_clocks(); + s5p6442_setup_clocks(); +} + +void __init s5p6442_init_irq(void) +{ + /* S5P6442 supports 3 VIC */ + u32 vic[3]; + + /* VIC0, VIC1, and VIC2: some interrupt reserved */ + vic[0] = 0x7fefffff; + vic[1] = 0X7f389c81; + vic[2] = 0X1bbbcfff; + + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +static struct sysdev_class s5p6442_sysclass = { + .name = "s5p6442-core", +}; + +static struct sys_device s5p6442_sysdev = { + .cls = &s5p6442_sysclass, +}; + +static int __init s5p6442_core_init(void) +{ + return sysdev_class_register(&s5p6442_sysclass); +} + +core_initcall(s5p6442_core_init); + +int __init s5p6442_init(void) +{ + printk(KERN_INFO "S5P6442: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5p6442_idle; + + return sysdev_register(&s5p6442_sysdev); +} diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S new file mode 100644 index 000000000000..bb6536147ffb --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/debug-macro.S @@ -0,0 +1,36 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> +#include <plat/regs-serial.h> + + .macro addruart, rx, rtmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S3C_PA_UART + ldrne \rx, = S3C_VA_UART +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +#define fifo_full fifo_full_s5pv210 +#define fifo_level fifo_level_s5pv210 + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s5p6442/include/mach/entry-macro.S b/arch/arm/mach-s5p6442/include/mach/entry-macro.S new file mode 100644 index 000000000000..6d574edbf1ae --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/entry-macro.S @@ -0,0 +1,48 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Low-level IRQ helper macros for the Samsung S5P6442 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <asm/hardware/vic.h> +#include <mach/map.h> +#include <plat/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, # S5P_IRQ_OFFSET + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + @ otherwise try vic2 + addeq \tmp, \base, #(VA_VIC2 - VA_VIC0) + addeq \irqnr, \irqnr, #32 + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-s5p6442/include/mach/gpio.h b/arch/arm/mach-s5p6442/include/mach/gpio.h new file mode 100644 index 000000000000..b8715df2fdab --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/gpio.h @@ -0,0 +1,123 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S5P6442_GPIO_A0_NR (8) +#define S5P6442_GPIO_A1_NR (2) +#define S5P6442_GPIO_B_NR (4) +#define S5P6442_GPIO_C0_NR (5) +#define S5P6442_GPIO_C1_NR (5) +#define S5P6442_GPIO_D0_NR (2) +#define S5P6442_GPIO_D1_NR (6) +#define S5P6442_GPIO_E0_NR (8) +#define S5P6442_GPIO_E1_NR (5) +#define S5P6442_GPIO_F0_NR (8) +#define S5P6442_GPIO_F1_NR (8) +#define S5P6442_GPIO_F2_NR (8) +#define S5P6442_GPIO_F3_NR (6) +#define S5P6442_GPIO_G0_NR (7) +#define S5P6442_GPIO_G1_NR (7) +#define S5P6442_GPIO_G2_NR (7) +#define S5P6442_GPIO_H0_NR (8) +#define S5P6442_GPIO_H1_NR (8) +#define S5P6442_GPIO_H2_NR (8) +#define S5P6442_GPIO_H3_NR (8) +#define S5P6442_GPIO_J0_NR (8) +#define S5P6442_GPIO_J1_NR (6) +#define S5P6442_GPIO_J2_NR (8) +#define S5P6442_GPIO_J3_NR (8) +#define S5P6442_GPIO_J4_NR (5) + +/* GPIO bank numbers */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ + +#define S5P6442_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + S5P6442_GPIO_A0_START = 0, + S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0), + S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1), + S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B), + S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0), + S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1), + S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0), + S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1), + S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0), + S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1), + S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0), + S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1), + S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2), + S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3), + S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0), + S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1), + S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2), + S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0), + S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1), + S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2), + S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3), + S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0), + S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1), + S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2), + S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3), +}; + +/* S5P6442 GPIO number definitions. */ +#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr)) +#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr)) +#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr)) +#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr)) +#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr)) +#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr)) +#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr)) +#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr)) +#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr)) +#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr)) +#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr)) +#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr)) +#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr)) +#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr)) +#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr)) +#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr)) +#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr)) +#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr)) +#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr)) +#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr)) +#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr)) +#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr)) +#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr)) +#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr)) +#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr)) + +/* the end of the S5P6442 specific gpios */ +#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1) +#define S3C_GPIO_END S5P6442_GPIO_END + +/* define the number of gpios we need to the one after the GPJ4() range */ +#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include <asm-generic/gpio.h> + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/hardware.h b/arch/arm/mach-s5p6442/include/mach/hardware.h new file mode 100644 index 000000000000..8cd7b67b49d4 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h new file mode 100644 index 000000000000..5d2195ad0b67 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/io.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5p6442/include/mach/io.h + * + * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> + * + * Default IO routines for S5P6442 + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* No current ISA/PCI bus support. */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#define IO_SPACE_LIMIT (0xFFFFFFFF) + +#endif diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h new file mode 100644 index 000000000000..da665809f6e4 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/irqs.h @@ -0,0 +1,86 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - IRQ definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H __FILE__ + +#include <plat/irqs.h> + +/* VIC0 */ +#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) +#define IRQ_BATF S5P_IRQ_VIC0(17) +#define IRQ_MDMA S5P_IRQ_VIC0(18) +#define IRQ_PDMA S5P_IRQ_VIC0(19) +#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) +#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) +#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) +#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) +#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) +#define IRQ_SYSTIMER S5P_IRQ_VIC0(26) +#define IRQ_WDT S5P_IRQ_VIC0(27) +#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) +#define IRQ_RTC_TIC S5P_IRQ_VIC0(29) +#define IRQ_GPIOINT S5P_IRQ_VIC0(30) + +/* VIC1 */ +#define IRQ_nPMUIRQ S5P_IRQ_VIC1(0) +#define IRQ_ONENAND S5P_IRQ_VIC1(7) +#define IRQ_UART0 S5P_IRQ_VIC1(10) +#define IRQ_UART1 S5P_IRQ_VIC1(11) +#define IRQ_UART2 S5P_IRQ_VIC1(12) +#define IRQ_SPI0 S5P_IRQ_VIC1(15) +#define IRQ_IIC S5P_IRQ_VIC1(19) +#define IRQ_IIC1 S5P_IRQ_VIC1(20) +#define IRQ_IIC2 S5P_IRQ_VIC1(21) +#define IRQ_OTG S5P_IRQ_VIC1(24) +#define IRQ_MSM S5P_IRQ_VIC1(25) +#define IRQ_HSMMC0 S5P_IRQ_VIC1(26) +#define IRQ_HSMMC1 S5P_IRQ_VIC1(27) +#define IRQ_HSMMC2 S5P_IRQ_VIC1(28) +#define IRQ_COMMRX S5P_IRQ_VIC1(29) +#define IRQ_COMMTX S5P_IRQ_VIC1(30) + +/* VIC2 */ +#define IRQ_LCD0 S5P_IRQ_VIC2(0) +#define IRQ_LCD1 S5P_IRQ_VIC2(1) +#define IRQ_LCD2 S5P_IRQ_VIC2(2) +#define IRQ_LCD3 S5P_IRQ_VIC2(3) +#define IRQ_ROTATOR S5P_IRQ_VIC2(4) +#define IRQ_FIMC0 S5P_IRQ_VIC2(5) +#define IRQ_FIMC1 S5P_IRQ_VIC2(6) +#define IRQ_FIMC2 S5P_IRQ_VIC2(7) +#define IRQ_JPEG S5P_IRQ_VIC2(8) +#define IRQ_3D S5P_IRQ_VIC2(10) +#define IRQ_Mixer S5P_IRQ_VIC2(11) +#define IRQ_MFC S5P_IRQ_VIC2(14) +#define IRQ_TVENC S5P_IRQ_VIC2(15) +#define IRQ_I2S0 S5P_IRQ_VIC2(16) +#define IRQ_I2S1 S5P_IRQ_VIC2(17) +#define IRQ_RP S5P_IRQ_VIC2(19) +#define IRQ_PCM0 S5P_IRQ_VIC2(20) +#define IRQ_PCM1 S5P_IRQ_VIC2(21) +#define IRQ_ADC S5P_IRQ_VIC2(23) +#define IRQ_PENDN S5P_IRQ_VIC2(24) +#define IRQ_KEYPAD S5P_IRQ_VIC2(25) +#define IRQ_SSS_INT S5P_IRQ_VIC2(27) +#define IRQ_SSS_HASH S5P_IRQ_VIC2(28) +#define IRQ_VIC_END S5P_IRQ_VIC2(31) + +#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) + +#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \ + (S5P_IRQ_EINT_BASE + (x)-16)) +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT(31) + 1) + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h new file mode 100644 index 000000000000..685277d792fb --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -0,0 +1,58 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/map.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> +#include <plat/map-s5p.h> + +#define S5P6442_PA_CHIPID (0xE0000000) +#define S5P_PA_CHIPID S5P6442_PA_CHIPID + +#define S5P6442_PA_SYSCON (0xE0100000) +#define S5P_PA_SYSCON S5P6442_PA_SYSCON + +#define S5P6442_PA_GPIO (0xE0200000) +#define S5P_PA_GPIO S5P6442_PA_GPIO + +#define S5P6442_PA_VIC0 (0xE4000000) +#define S5P_PA_VIC0 S5P6442_PA_VIC0 + +#define S5P6442_PA_VIC1 (0xE4100000) +#define S5P_PA_VIC1 S5P6442_PA_VIC1 + +#define S5P6442_PA_VIC2 (0xE4200000) +#define S5P_PA_VIC2 S5P6442_PA_VIC2 + +#define S5P6442_PA_TIMER (0xEA000000) +#define S5P_PA_TIMER S5P6442_PA_TIMER + +#define S5P6442_PA_SYSTIMER (0xEA100000) + +#define S5P6442_PA_UART (0xEC000000) + +#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) +#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400) +#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800) +#define S5P_SZ_UART SZ_256 + +#define S5P6442_PA_IIC0 (0xEC100000) + +#define S5P6442_PA_SDRAM (0x20000000) +#define S5P_PA_SDRAM S5P6442_PA_SDRAM + +/* compatibiltiy defines. */ +#define S3C_PA_UART S5P6442_PA_UART +#define S3C_PA_IIC S5P6442_PA_IIC0 + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h new file mode 100644 index 000000000000..9ddd877ba2ea --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/memory.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/memory.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x20000000) +#define CONSISTENT_DMA_SIZE SZ_8M + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h new file mode 100644 index 000000000000..15e8525da0f1 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h @@ -0,0 +1,69 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Copyright 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h + * + * S5P6442 - pwm clock and timer support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_PWMCLK_H +#define __ASM_ARCH_PWMCLK_H __FILE__ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @cfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C2410_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << (1 + tcfg1); +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 0; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div) - 1; +} + +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK + +#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h new file mode 100644 index 000000000000..d8360b5d4ece --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h @@ -0,0 +1,103 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include <mach/map.h> + +#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x08) +#define S5P_EPLL_LOCK S5P_CLKREG(0x10) +#define S5P_VPLL_LOCK S5P_CLKREG(0x20) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x108) +#define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_VPLL_CON S5P_CLKREG(0x120) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) +#define S5P_CLK_SRC4 S5P_CLKREG(0x210) +#define S5P_CLK_SRC5 S5P_CLKREG(0x214) +#define S5P_CLK_SRC6 S5P_CLKREG(0x218) + +#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) +#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) +#define S5P_CLK_DIV5 S5P_CLKREG(0x314) +#define S5P_CLK_DIV6 S5P_CLKREG(0x318) + +#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) + +/* CLK_OUT */ +#define S5P_CLK_OUT_SHIFT (12) +#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT) +#define S5P_CLK_OUT S5P_CLKREG(0x500) + +#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000) +#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004) + +#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100) +#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104) + +#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) + +/* Register Bit definition */ +#define S5P_EPLL_EN (1<<31) +#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_APLL_SHIFT (0) +#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) +#define S5P_CLKDIV0_A2M_SHIFT (4) +#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) +#define S5P_CLKDIV0_D0CLK_SHIFT (16) +#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT) +#define S5P_CLKDIV0_P0CLK_SHIFT (20) +#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT) +#define S5P_CLKDIV0_D1CLK_SHIFT (24) +#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT) +#define S5P_CLKDIV0_P1CLK_SHIFT (28) +#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT) + +/* Clock MUX status Registers */ +#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0) +#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT) +#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4) +#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8) +#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12) +#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16) +#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20) +#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT) +#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24) +#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT) +#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24) +#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT) +#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28) +#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/regs-irq.h b/arch/arm/mach-s5p6442/include/mach/regs-irq.h new file mode 100644 index 000000000000..73782b52a83b --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/regs-irq.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include <asm/hardware/vic.h> +#include <mach/map.h> + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h new file mode 100644 index 000000000000..8bcd8ed0c3c3 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/system.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/system.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode, const char *cmd) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h new file mode 100644 index 000000000000..e1d4cabf8297 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/tick.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/tick.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on arch/arm/mach-s3c6400/include/mach/tick.h + * + * S5P6442 - Timer tick support definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/timex.h b/arch/arm/mach-s5p6442/include/mach/timex.h new file mode 100644 index 000000000000..ff8f2fcadeb7 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/timex.h @@ -0,0 +1,24 @@ +/* arch/arm/mach-s5p6442/include/mach/timex.h + * + * Copyright (c) 2003-2010 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S5P6442 - time parameters + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it + * a variable is useless. It seems as long as we make our timers an + * exact multiple of HZ, any value that makes a 1->1 correspondence + * for the time conversion functions to/from jiffies is acceptable. +*/ + +#define CLOCK_TICK_RATE 12000000 + +#endif /* __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/uncompress.h b/arch/arm/mach-s5p6442/include/mach/uncompress.h new file mode 100644 index 000000000000..5ac7cbeeb987 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/uncompress.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6442 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h new file mode 100644 index 000000000000..be3333688c20 --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h @@ -0,0 +1,17 @@ +/* arch/arm/mach-s5p6442/include/mach/vmalloc.h + * + * Copyright 2010 Ben Dooks <ben-linux@fluff.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S5P6442 vmalloc definition +*/ + +#ifndef __ASM_ARCH_VMALLOC_H +#define __ASM_ARCH_VMALLOC_H + +#define VMALLOC_END (0xE0000000) + +#endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5p6442/init.c b/arch/arm/mach-s5p6442/init.c new file mode 100644 index 000000000000..1874bdb71e1d --- /dev/null +++ b/arch/arm/mach-s5p6442/init.c @@ -0,0 +1,44 @@ +/* linux/arch/arm/mach-s5p6442/s5p6442-init.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/s5p6442.h> +#include <plat/regs-serial.h> + +static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = { + [0] = { + .name = "pclk", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, +}; + +/* uart registration process */ +void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + struct s3c2410_uartcfg *tcfg = cfg; + u32 ucnt; + + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + if (!tcfg->clocks) { + tcfg->clocks = s5p6442_serial_clocks; + tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks); + } + } + + s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c new file mode 100644 index 000000000000..0d63371ce07c --- /dev/null +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c @@ -0,0 +1,91 @@ +/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> + +#include <plat/regs-serial.h> +#include <plat/s5p6442.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5P6442_UCON_DEFAULT, + .ulcon = S5P6442_ULCON_DEFAULT, + .ufcon = S5P6442_UFCON_DEFAULT, + }, +}; + +static struct platform_device *smdk6442_devices[] __initdata = { +}; + +static void __init smdk6442_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs)); +} + +static void __init smdk6442_machine_init(void) +{ + platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices)); +} + +MACHINE_START(SMDK6442, "SMDK6442") + /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = s5p6442_init_irq, + .map_io = smdk6442_map_io, + .init_machine = smdk6442_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END |