diff options
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
22 files changed, 229 insertions, 340 deletions
diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml index 444aeea27db8..eb241587efd1 100644 --- a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -89,6 +89,8 @@ required: - compatible - clocks +additionalProperties: false + examples: - | vco1: clock { diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml index 2821425ee445..bd4cefbb1244 100644 --- a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml +++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml @@ -134,7 +134,11 @@ properties: "#reset-cells": const: 1 -unevaluatedProperties: false + clocks: true + + clock-names: true + +additionalProperties: false required: - compatible diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml index 97131bfa6f87..624984d51c10 100644 --- a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml +++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml @@ -101,7 +101,7 @@ properties: clock-names: const: ref_clk -unevaluatedProperties: false +additionalProperties: false required: - compatible diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index 28c6461b9a9a..2ac1131fd922 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -50,6 +50,15 @@ properties: '#clock-cells': const: 1 + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: [ xin, clkin ] + clocks: + minItems: 1 + maxItems: 2 + patternProperties: "^OUT[1-4]$": type: object @@ -93,19 +102,12 @@ allOf: maxItems: 1 else: # Devices without builtin crystal - properties: - clock-names: - minItems: 1 - maxItems: 2 - items: - enum: [ xin, clkin ] - clocks: - minItems: 1 - maxItems: 2 required: - clock-names - clocks +additionalProperties: false + examples: - | #include <dt-bindings/clk/versaclock.h> diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.yaml b/Documentation/devicetree/bindings/clock/imx23-clock.yaml index ad21899981af..5e296a00e14f 100644 --- a/Documentation/devicetree/bindings/clock/imx23-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx23-clock.yaml @@ -87,6 +87,8 @@ examples: serial@8006c000 { compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; + interrupts = <24>; clocks = <&clks 32>; + dmas = <&dma_apbx 6>, <&dma_apbx 7>; + dma-names = "rx", "tx"; }; diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.yaml b/Documentation/devicetree/bindings/clock/imx28-clock.yaml index f1af1108129e..f831b780f951 100644 --- a/Documentation/devicetree/bindings/clock/imx28-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx28-clock.yaml @@ -108,8 +108,10 @@ examples: }; serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + compatible = "fsl,imx28-auart"; reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; + interrupts = <112>; + dmas = <&dma_apbx 8>, <&dma_apbx 9>; + dma-names = "rx", "tx"; clocks = <&clks 45>; }; diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml index 92a8e545e212..4f4637eddb8b 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -57,6 +57,8 @@ required: - interrupts - '#clock-cells' +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml index c97bf95b4150..b83c8f43d664 100644 --- a/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.yaml @@ -33,6 +33,8 @@ required: - interrupts - '#clock-cells' +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml index de48924be191..484894a4b23f 100644 --- a/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.yaml @@ -49,6 +49,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml index e50cddee43c3..e6c795657c24 100644 --- a/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.yaml @@ -53,6 +53,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml index 36ce7667c972..6a51a3f51cd9 100644 --- a/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.yaml @@ -49,6 +49,8 @@ required: - clocks - clock-names +additionalProperties: false + examples: # Clock Control Module node: - | diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml new file mode 100644 index 000000000000..625f573a7b90 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Family Clock Control Module Binding + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +description: | + NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock + controller, which generates and supplies to all modules. + +properties: + compatible: + enum: + - fsl,imx8mm-ccm + - fsl,imx8mn-ccm + - fsl,imx8mp-ccm + - fsl,imx8mq-ccm + + reg: + maxItems: 1 + + clocks: + minItems: 6 + maxItems: 7 + + clock-names: + minItems: 6 + maxItems: 7 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h + for the full list of i.MX8M clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-ccm + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + clock-names: + minItems: 7 + maxItems: 7 + items: + - const: ckil + - const: osc_25m + - const: osc_27m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ext1 clock input + - description: ext2 clock input + - description: ext3 clock input + - description: ext4 clock input + + clock-names: + items: + - const: osc_32k + - const: osc_24m + - const: clk_ext1 + - const: clk_ext2 + - const: clk_ext3 + - const: clk_ext4 + +additionalProperties: false + +examples: + # Clock Control Module node: + - | + clock-controller@30380000 { + compatible = "fsl,imx8mm-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + }; + + - | + clock-controller@30390000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, + <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; + clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml deleted file mode 100644 index ec830db1367b..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mm-clock.yaml +++ /dev/null @@ -1,68 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP i.MX8M Mini Clock Control Module Binding - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: | - NXP i.MX8M Mini clock control module is an integrated clock controller, which - generates and supplies to all modules. - -properties: - compatible: - const: fsl,imx8mm-ccm - - reg: - maxItems: 1 - - clocks: - items: - - description: 32k osc - - description: 24m osc - - description: ext1 clock input - - description: ext2 clock input - - description: ext3 clock input - - description: ext4 clock input - - clock-names: - items: - - const: osc_32k - - const: osc_24m - - const: clk_ext1 - - const: clk_ext2 - - const: clk_ext3 - - const: clk_ext4 - - '#clock-cells': - const: 1 - description: - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h - for the full list of i.MX8M Mini clock IDs. - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - -examples: - # Clock Control Module node: - - | - clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - }; - -... diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml deleted file mode 100644 index bdaa29616ab1..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml +++ /dev/null @@ -1,70 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP i.MX8M Nano Clock Control Module Binding - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: | - NXP i.MX8M Nano clock control module is an integrated clock controller, which - generates and supplies to all modules. - -properties: - compatible: - const: fsl,imx8mn-ccm - - reg: - maxItems: 1 - - clocks: - items: - - description: 32k osc - - description: 24m osc - - description: ext1 clock input - - description: ext2 clock input - - description: ext3 clock input - - description: ext4 clock input - - clock-names: - items: - - const: osc_32k - - const: osc_24m - - const: clk_ext1 - - const: clk_ext2 - - const: clk_ext3 - - const: clk_ext4 - - '#clock-cells': - const: 1 - description: - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h - for the full list of i.MX8M Nano clock IDs. - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - -additionalProperties: false - -examples: - # Clock Control Module node: - - | - clk: clock-controller@30380000 { - compatible = "fsl,imx8mn-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, - <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", - "clk_ext2", "clk_ext3", "clk_ext4"; - }; - -... diff --git a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml deleted file mode 100644 index 4351a1dbb4f7..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml +++ /dev/null @@ -1,70 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP i.MX8M Plus Clock Control Module Binding - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: - NXP i.MX8M Plus clock control module is an integrated clock controller, which - generates and supplies to all modules. - -properties: - compatible: - const: fsl,imx8mp-ccm - - reg: - maxItems: 1 - - clocks: - items: - - description: 32k osc - - description: 24m osc - - description: ext1 clock input - - description: ext2 clock input - - description: ext3 clock input - - description: ext4 clock input - - clock-names: - items: - - const: osc_32k - - const: osc_24m - - const: clk_ext1 - - const: clk_ext2 - - const: clk_ext3 - - const: clk_ext4 - - '#clock-cells': - const: 1 - description: - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h - for the full list of i.MX8M Plus clock IDs. - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - -additionalProperties: false - -examples: - # Clock Control Module node: - - | - clk: clock-controller@30380000 { - compatible = "fsl,imx8mp-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, - <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", - "clk_ext2", "clk_ext3", "clk_ext4"; - }; - -... diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml deleted file mode 100644 index 05d7d1471e0c..000000000000 --- a/Documentation/devicetree/bindings/clock/imx8mq-clock.yaml +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP i.MX8M Quad Clock Control Module Binding - -maintainers: - - Anson Huang <Anson.Huang@nxp.com> - -description: | - NXP i.MX8M Quad clock control module is an integrated clock controller, which - generates and supplies to all modules. - -properties: - compatible: - const: fsl,imx8mq-ccm - - reg: - maxItems: 1 - - clocks: - items: - - description: 32k osc - - description: 25m osc - - description: 27m osc - - description: ext1 clock input - - description: ext2 clock input - - description: ext3 clock input - - description: ext4 clock input - - clock-names: - items: - - const: ckil - - const: osc_25m - - const: osc_27m - - const: clk_ext1 - - const: clk_ext2 - - const: clk_ext3 - - const: clk_ext4 - - '#clock-cells': - const: 1 - description: - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h - for the full list of i.MX8M Quad clock IDs. - -required: - - compatible - - reg - - clocks - - clock-names - - '#clock-cells' - -examples: - # Clock Control Module node: - - | - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - }; - -... diff --git a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml index 6dc1414bfb7f..f3e1a700a2ca 100644 --- a/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml +++ b/Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml @@ -33,6 +33,8 @@ required: - reg - '#clock-cells' +additionalProperties: false + examples: - | cgu: clock-controller@e0200000 { diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml index a5766ff89082..80bd6caf5bc9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -56,6 +56,8 @@ required: - '#reset-cells' - '#power-domain-cells' +additionalProperties: false + examples: - | #include <dt-bindings/clock/qcom,rpmh.h> diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f4fb8c..000000000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,<chip>-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 000000000000..c3be1b600007 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Sagar Kadam <sagar.kadam@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu540-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml index c6d091518650..4069e09cb62d 100644 --- a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -73,6 +73,8 @@ else: The 'reg' property for the clock node is also required if there is a sub range of registers for the clocks. +additionalProperties: false + examples: - | ap_clk: clock-controller@21500000 { diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml index 869b18ac88d7..6b419a9878f3 100644 --- a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -26,6 +26,8 @@ required: - "#clock-cells" - reg +additionalProperties: false + examples: - | ehrpwm_tbclk: syscon@4140 { |