diff options
| -rw-r--r-- | drivers/edac/amd64_edac.c | 44 | ||||
| -rw-r--r-- | drivers/edac/amd64_edac.h | 11 |
2 files changed, 54 insertions, 1 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 870f56713c22..bb70392bb115 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1210,6 +1210,19 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt) return channels; } +static int f17_early_channel_count(struct amd64_pvt *pvt) +{ + int i, channels = 0; + + /* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */ + for (i = 0; i < NUM_UMCS; i++) + channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); + + amd64_info("MCT channel count: %d\n", channels); + + return channels; +} + static int ddr3_cs_size(unsigned i, bool dct_width) { unsigned shift = 0; @@ -1337,6 +1350,23 @@ static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, return ddr3_cs_size(cs_mode, false); } +static int f17_base_addr_to_cs_size(struct amd64_pvt *pvt, u8 umc, + unsigned int cs_mode, int csrow_nr) +{ + u32 base_addr = pvt->csels[umc].csbases[csrow_nr]; + + /* Each mask is used for every two base addresses. */ + u32 addr_mask = pvt->csels[umc].csmasks[csrow_nr >> 1]; + + /* Register [31:1] = Address [39:9]. Size is in kBs here. */ + u32 size = ((addr_mask >> 1) - (base_addr >> 1) + 1) >> 1; + + edac_dbg(1, "BaseAddr: 0x%x, AddrMask: 0x%x\n", base_addr, addr_mask); + + /* Return size in MBs. */ + return size >> 10; +} + static void read_dram_ctl_register(struct amd64_pvt *pvt) { @@ -1989,6 +2019,15 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f16_dbam_to_chip_select, } }, + [F17_CPUS] = { + .ctl_name = "F17h", + .f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0, + .f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_base_addr_to_cs_size, + } + }, }; /* @@ -2790,6 +2829,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) pvt->ops = &family_types[F16_CPUS].ops; break; + case 0x17: + fam_type = &family_types[F17_CPUS]; + pvt->ops = &family_types[F17_CPUS].ops; + break; + default: amd64_err("Unsupported family!\n"); return NULL; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 96c1f5d6d130..ada39f165a9b 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -118,6 +118,8 @@ #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 +#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 +#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 /* * Function 1 - Address Map @@ -266,6 +268,7 @@ enum amd_families { F15_M60H_CPUS, F16_CPUS, F16_M30H_CPUS, + F17_CPUS, NUM_FAMILIES, }; @@ -298,6 +301,10 @@ struct chip_select { u8 m_cnt; }; +struct amd64_umc { + u32 sdp_ctrl; /* SDP Control reg */ +}; + struct amd64_pvt { struct low_ops *ops; @@ -345,6 +352,8 @@ struct amd64_pvt { /* cache the dram_type */ enum mem_type dram_type; + + struct amd64_umc *umc; /* UMC registers */ }; enum err_codes { @@ -438,7 +447,7 @@ struct low_ops { struct amd64_family_type { const char *ctl_name; - u16 f1_id, f2_id; + u16 f0_id, f1_id, f2_id, f6_id; struct low_ops ops; }; |