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| author | Zeng Guang <guang.zeng@intel.com> | 2022-04-19 23:35:16 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-06-08 04:47:23 -0400 |
| commit | 5413bcba7ed57206178d60ee03dd5bb3a460e645 (patch) | |
| tree | 1ec92e8a1ce1745f06014d4b7aa3083999878060 /virt | |
| parent | 0b85baa5f46de1c6ad6e4b987905df041f2f80f0 (diff) | |
| download | lwn-5413bcba7ed57206178d60ee03dd5bb3a460e645.tar.gz lwn-5413bcba7ed57206178d60ee03dd5bb3a460e645.zip | |
KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode
Upcoming Intel CPUs will support virtual x2APIC MSR writes to the vICR,
i.e. will trap and generate an APIC-write VM-Exit instead of intercepting
the WRMSR. Add support for handling "nodecode" x2APIC writes, which
were previously impossible.
Note, x2APIC MSR writes are 64 bits wide.
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Message-Id: <20220419153516.11739-1-guang.zeng@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions