diff options
author | Nick Forrington <nick.forrington@arm.com> | 2022-05-20 19:14:43 +0100 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-05-23 10:13:29 -0300 |
commit | ee2409510cf41556bd5d108711e08d0c6e9e8c23 (patch) | |
tree | c7926c15d8f78308d461c3127fe68171f461d4f2 /tools/perf | |
parent | d8fc08550929bb845c13cfefcc632a69fcf79b2c (diff) | |
download | lwn-ee2409510cf41556bd5d108711e08d0c6e9e8c23.tar.gz lwn-ee2409510cf41556bd5d108711e08d0c6e9e8c23.zip |
perf vendors events arm64: Arm Cortex-A34
Add PMU events for Arm Cortex-A34
Add corresponding common events
Update mapfile.csv
Event data based on:
https://github.com/ARM-software/data/tree/master/pmu/cortex-a34.json
which is based on PMU event descriptions from the Arm Cortex-A34 Technical
Reference Manual.
Common event data based on:
https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json
which is based on PMU event descriptions found in the Arm Architecture
Reference Manual:
https://developer.arm.com/documentation/ddi0487/
Mapping data (for mapfile.csv) based on:
https://github.com/ARM-software/data/blob/master/cpus.json
which is based on Main ID Register (MIDR) information found in the Arm
Technical Reference Manuals for individual CPUs.
Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Nick Forrington <nick.forrington@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220520181455.340344-2-nick.forrington@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf')
8 files changed, 148 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json new file mode 100644 index 000000000000..7c018f439206 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json index 80d7a70829a0..20923bf10adc 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -36,6 +36,18 @@ "BriefDescription": "Attributable Level 1 data TLB refill" }, { + "PublicDescription": "Instruction architecturally executed, condition code check pass, load", + "EventCode": "0x06", + "EventName": "LD_RETIRED", + "BriefDescription": "Instruction architecturally executed, condition code check pass, load" + }, + { + "PublicDescription": "Instruction architecturally executed, condition code check pass, store", + "EventCode": "0x07", + "EventName": "ST_RETIRED", + "BriefDescription": "Instruction architecturally executed, condition code check pass, store" + }, + { "PublicDescription": "Instruction architecturally executed", "EventCode": "0x08", "EventName": "INST_RETIRED", @@ -60,6 +72,30 @@ "BriefDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" }, { + "PublicDescription": "Instruction architecturally executed, condition code check pass, software change of the PC", + "EventCode": "0x0C", + "EventName": "PC_WRITE_RETIRED", + "BriefDescription": "Instruction architecturally executed, condition code check pass, software change of the PC" + }, + { + "PublicDescription": "Instruction architecturally executed, immediate branch", + "EventCode": "0x0D", + "EventName": "BR_IMMED_RETIRED", + "BriefDescription": "Instruction architecturally executed, immediate branch" + }, + { + "PublicDescription": "Instruction architecturally executed, condition code check pass, procedure return", + "EventCode": "0x0E", + "EventName": "BR_RETURN_RETIRED", + "BriefDescription": "Instruction architecturally executed, condition code check pass, procedure return" + }, + { + "PublicDescription": "Instruction architecturally executed, condition code check pass, unaligned", + "EventCode": "0x0F", + "EventName": "UNALIGNED_LDST_RETIRED", + "BriefDescription": "Instruction architecturally executed, condition code check pass, unaligned" + }, + { "PublicDescription": "Mispredicted or not predicted branch speculatively executed", "EventCode": "0x10", "EventName": "BR_MIS_PRED", diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index b899db48c12a..461bb8b845d6 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,6 +12,7 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd020,v1,arm/cortex-a34,core 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core |