diff options
| author | Trevor Wu <trevor.wu@mediatek.com> | 2022-02-21 13:57:16 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-02-21 13:24:56 +0000 |
| commit | ff5a90173d981934e1134d28af3625acaab01d80 (patch) | |
| tree | 9087952e0f1340f62871bec4d8edfb59512ac601 /sound/soc/mediatek/mt8195/mt8195-afe-clk.h | |
| parent | b9afe038b1fba24e815000606d5877de97f9f154 (diff) | |
| download | lwn-ff5a90173d981934e1134d28af3625acaab01d80.tar.gz lwn-ff5a90173d981934e1134d28af3625acaab01d80.zip | |
ASoC: mediatek: mt8195: enable apll tuner
Normally, the clock source of audio module is either 26M or APLL1/APLL2,
but APLL1/APLL2 are not the multiple of 26M.
In the patch, APLL1 and APLL2 tuners are enabled to handle sample rate
mismatch when the data path crosses two different clock domains.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://lore.kernel.org/r/20220221055716.18580-1-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/mediatek/mt8195/mt8195-afe-clk.h')
| -rw-r--r-- | sound/soc/mediatek/mt8195/mt8195-afe-clk.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h index f8e6eeb29a89..40663e31becd 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.h +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.h @@ -35,6 +35,8 @@ enum { MT8195_CLK_INFRA_AO_AUDIO_26M_B, MT8195_CLK_SCP_ADSP_AUDIODSP, MT8195_CLK_AUD_AFE, + MT8195_CLK_AUD_APLL1_TUNER, + MT8195_CLK_AUD_APLL2_TUNER, MT8195_CLK_AUD_APLL, MT8195_CLK_AUD_APLL2, MT8195_CLK_AUD_DAC, @@ -84,6 +86,15 @@ enum { MT8195_MCK_SEL_NUM, }; +enum { + MT8195_AUD_PLL1, + MT8195_AUD_PLL2, + MT8195_AUD_PLL3, + MT8195_AUD_PLL4, + MT8195_AUD_PLL5, + MT8195_AUD_PLL_NUM, +}; + struct mtk_base_afe; int mt8195_afe_get_mclk_source_clk_id(int sel); |