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| author | Dharageswari R <dharageswari.r@intel.com> | 2016-06-03 18:29:37 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-06-07 14:19:11 +0100 |
| commit | 51a01b8c2ea632ed9a57f98c234a0cd9dafe181a (patch) | |
| tree | 7c13c502568b2af9cfce3f34f477deaeaad586d4 /sound/soc/intel/skylake/skl.h | |
| parent | 1ae7ca041a460502b0f9877d84d0f0d9bed9cb72 (diff) | |
| download | lwn-51a01b8c2ea632ed9a57f98c234a0cd9dafe181a.tar.gz lwn-51a01b8c2ea632ed9a57f98c234a0cd9dafe181a.zip | |
ASoC: Intel: Skylake: Disable SRAM Retention before D3
SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention
feature,otherwise it may lead to SRAM ECC Errors.
Signed-off-by: Dharageswari R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/skylake/skl.h')
| -rw-r--r-- | sound/soc/intel/skylake/skl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index f66be173f86b..25b8d4897ff5 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -48,6 +48,8 @@ #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 +#define AZX_PCIREG_PGCTL 0x44 +#define AZX_PGCTL_LSRMD_MASK (1 << 4) #define AZX_PCIREG_CGCTL 0x48 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) |