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authorBard Liao <bardliao@realtek.com>2018-05-17 13:54:08 +0800
committerMark Brown <broonie@kernel.org>2018-05-17 18:10:41 +0100
commit81dd1c5dcf510a2104b3468e9c4884f85ef1f644 (patch)
tree6a3c188e28562f34880c388e46de5ed540521a4c /sound/soc/codecs/rt5670.c
parent74f24d8728ef12276d58e3d73283cc1d76db7507 (diff)
downloadlwn-81dd1c5dcf510a2104b3468e9c4884f85ef1f644.tar.gz
lwn-81dd1c5dcf510a2104b3468e9c4884f85ef1f644.zip
ASoC: rt5670: improve PLL function's stability
Set PR-38 register to 0x1fe1 will make PLL function more stable. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/rt5670.c')
-rw-r--r--sound/soc/codecs/rt5670.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c
index dc7df337d5f8..732ef928b25d 100644
--- a/sound/soc/codecs/rt5670.c
+++ b/sound/soc/codecs/rt5670.c
@@ -71,7 +71,7 @@ static const struct regmap_range_cfg rt5670_ranges[] = {
static const struct reg_sequence init_list[] = {
{ RT5670_PR_BASE + 0x14, 0x9a8a },
- { RT5670_PR_BASE + 0x38, 0x3ba1 },
+ { RT5670_PR_BASE + 0x38, 0x1fe1 },
{ RT5670_PR_BASE + 0x3d, 0x3640 },
{ 0x8a, 0x0123 },
};