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authorMohan Kumar <mkumard@nvidia.com>2020-08-05 15:22:19 +0530
committerTakashi Iwai <tiwai@suse.de>2020-08-05 12:27:35 +0200
commit6c17e9dd5cdd352276180f47c0a8b24a1d4661af (patch)
tree7f85bb3c6604ec5e48ffb10006d71c2f3f16831a /sound/pci/hda
parent80982c7e834e5d4e325b6ce33757012ecafdf0bb (diff)
downloadlwn-6c17e9dd5cdd352276180f47c0a8b24a1d4661af.tar.gz
lwn-6c17e9dd5cdd352276180f47c0a8b24a1d4661af.zip
ASoC: hda/tegra: Set buffer alignment to 128 bytes
Set chip->align_buffer_size to 1 for Tegra platforms to make the buffer alignment to be multiple of 128 bytes. This fix is applied as gstreamer alsasink gets stuck with the default buffer-time and latency-time parameters with 4 byte buffer alignment. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Link: https://lore.kernel.org/r/20200805095221.5476-2-mkumard@nvidia.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda')
-rw-r--r--sound/pci/hda/hda_tegra.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c
index 5637f0129932..ecf98eb9df36 100644
--- a/sound/pci/hda/hda_tegra.c
+++ b/sound/pci/hda/hda_tegra.c
@@ -333,6 +333,8 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
gcap = azx_readw(chip, GCAP);
dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
+ chip->align_buffer_size = 1;
+
/* read number of streams from GCAP register instead of using
* hardcoded value
*/