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author | Boqun Feng <boqun.feng@gmail.com> | 2015-11-02 09:30:31 +0800 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-01-31 11:29:03 -0800 |
commit | 2ed6c101147879faa253fdf045d87651a6cb8f18 (patch) | |
tree | 3c4a15d19cadb63e943f954d739e39643a8ffbe1 /scripts | |
parent | e924c60db1b4891e45d15a33474ac5fab62cf029 (diff) | |
download | lwn-2ed6c101147879faa253fdf045d87651a6cb8f18.tar.gz lwn-2ed6c101147879faa253fdf045d87651a6cb8f18.zip |
powerpc: Make value-returning atomics fully ordered
commit 49e9cf3f0c04bf76ffa59242254110309554861d upstream.
According to memory-barriers.txt:
> Any atomic operation that modifies some state in memory and returns
> information about the state (old or new) implies an SMP-conditional
> general memory barrier (smp_mb()) on each side of the actual
> operation ...
Which mean these operations should be fully ordered. However on PPC,
PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
which is currently "lwsync" if SMP=y. The leading "lwsync" can not
guarantee fully ordered atomics, according to Paul Mckenney:
https://lkml.org/lkml/2015/10/14/970
To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
the fully-ordered semantics.
This also makes futex atomics fully ordered, which can avoid possible
memory ordering problems if userspace code relies on futex system call
for fully ordered semantics.
Fixes: b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions