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| author | Boqun Feng <boqun.feng@gmail.com> | 2015-11-02 09:30:32 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-01-31 11:29:03 -0800 |
| commit | badc688439f09f440e8d3dcd5d23457e54dfa8eb (patch) | |
| tree | f91ef937d036b0f48479ddd99aadf48f311aeeac /scripts/recordmcount.pl | |
| parent | 2ed6c101147879faa253fdf045d87651a6cb8f18 (diff) | |
| download | lwn-badc688439f09f440e8d3dcd5d23457e54dfa8eb.tar.gz lwn-badc688439f09f440e8d3dcd5d23457e54dfa8eb.zip | |
powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
commit 81d7a3294de7e9828310bbf986a67246b13fa01e upstream.
According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
versions all need to be fully ordered, however they are now just
RELEASE+ACQUIRE, which are not fully ordered.
So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
__{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
This patch depends on patch "powerpc: Make value-returning atomics fully
ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts/recordmcount.pl')
0 files changed, 0 insertions, 0 deletions