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| author | Steve Capper <steve.capper@linaro.org> | 2014-07-02 11:46:23 +0100 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2014-07-18 15:51:01 +0200 |
| commit | 53d968cadf757d911ed4ad7f935007bff1e1e509 (patch) | |
| tree | 714e3a2311b6b7c756e43177d1ef948b01620f17 /mm/mmu_context.c | |
| parent | 6b5002673d4de9144db56cfe17046b3873cc6d9e (diff) | |
| download | lwn-53d968cadf757d911ed4ad7f935007bff1e1e509.tar.gz lwn-53d968cadf757d911ed4ad7f935007bff1e1e509.zip | |
arm64: mm: Make icache synchronisation logic huge page aware
commit 923b8f5044da753e4985ab15c1374ced2cdf616c upstream.
The __sync_icache_dcache routine will only flush the dcache for the
first page of a compound page, potentially leading to stale icache
data residing further on in a hugetlb page.
This patch addresses this issue by taking into consideration the
order of the page when flushing the dcache.
Reported-by: Mark Brown <broonie@linaro.org>
Tested-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'mm/mmu_context.c')
0 files changed, 0 insertions, 0 deletions