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author | Jan Beulich <jbeulich@novell.com> | 2007-02-13 13:26:23 +0100 |
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committer | Andi Kleen <andi@basil.nowhere.org> | 2007-02-13 13:26:23 +0100 |
commit | 24ce0e96f2dea558762c994d054ea2f3c01fa95a (patch) | |
tree | 59a4a538e6d67d0a15751095c6b191010be04f4f /kernel | |
parent | 9b355897562fe2291248a7aec8e479c2c98cf117 (diff) | |
download | lwn-24ce0e96f2dea558762c994d054ea2f3c01fa95a.tar.gz lwn-24ce0e96f2dea558762c994d054ea2f3c01fa95a.zip |
[PATCH] x86-64: Tighten mce_amd driver MSR reads
while debugging an unrelated problem in Xen, I noticed odd reads from
non-existent MSRs. Having now found time to look why these happen, I
came up with below patch, which
- prevents accessing MCi_MISCj with j > 0 when the block pointer in
MCi_MISC0 is zero
- accesses only contiguous MCi_MISCj until a non-implemented one is
found
- doesn't touch unimplemented blocks in mce_threshold_interrupt at all
- gives names to two bits previously derived from MASK_VALID_HI (it
took me some time to understand the code without this)
The first three items, besides being apparently closer to the spec, should
namely help cutting down on the time mce_threshold_interrupt() takes.
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions