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| author | Andre Przywara <andre.przywara@arm.com> | 2014-11-12 13:46:06 +0000 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2016-06-19 23:47:43 -0400 |
| commit | 045f08909af86b12a5030c5ce34bb15f9a201bed (patch) | |
| tree | 65fc59ebf6491dd8fba277d1e3f9301458c79b6d /include | |
| parent | 26c6a77797c961c345b3d9c2be96f2cbde6276a1 (diff) | |
| download | lwn-045f08909af86b12a5030c5ce34bb15f9a201bed.tar.gz lwn-045f08909af86b12a5030c5ce34bb15f9a201bed.zip | |
arm64: GICv3: introduce symbolic names for GICv3 ICC_SGI1R_EL1 fields
[ Upstream commit 7e5802781c3e109558ddfd8b02155ad24d872ee7 ]
The gic_send_sgi() function used hardcoded bit shift values to
generate the ICC_SGI1R_EL1 register value.
Replace this with symbolic names to allow reusing them later.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 03a4ea37ba86..f53d36d8f01e 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -142,6 +142,18 @@ #define ICC_SRE_EL2_SRE (1 << 0) #define ICC_SRE_EL2_ENABLE (1 << 3) +#define ICC_SGI1R_TARGET_LIST_SHIFT 0 +#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) +#define ICC_SGI1R_AFFINITY_1_SHIFT 16 +#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) +#define ICC_SGI1R_SGI_ID_SHIFT 24 +#define ICC_SGI1R_SGI_ID_MASK (0xff << ICC_SGI1R_SGI_ID_SHIFT) +#define ICC_SGI1R_AFFINITY_2_SHIFT 32 +#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) +#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 +#define ICC_SGI1R_AFFINITY_3_SHIFT 48 +#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) + /* * System register definitions */ |