diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-31 13:37:27 +1100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-31 13:37:27 +1100 |
| commit | 8af03e782cae1e0a0f530ddd22301cdd12cf9dc0 (patch) | |
| tree | c4af13a38bd3cc1a811a37f2358491f171052070 /include | |
| parent | 6232665040f9a23fafd9d94d4ae8d5a2dc850f65 (diff) | |
| parent | 99e139126ab2e84be67969650f92eb37c12ab5cd (diff) | |
| download | lwn-8af03e782cae1e0a0f530ddd22301cdd12cf9dc0.tar.gz lwn-8af03e782cae1e0a0f530ddd22301cdd12cf9dc0.zip | |
Merge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (454 commits)
[POWERPC] Cell IOMMU fixed mapping support
[POWERPC] Split out the ioid fetching/checking logic
[POWERPC] Add support to cell_iommu_setup_page_tables() for multiple windows
[POWERPC] Split out the IOMMU logic from cell_dma_dev_setup()
[POWERPC] Split cell_iommu_setup_hardware() into two parts
[POWERPC] Split out the logic that allocates struct iommus
[POWERPC] Allocate the hash table under 1G on cell
[POWERPC] Add set_dma_ops() to match get_dma_ops()
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
[POWERPC] 85xx: Only invalidate TLB0 and TLB1
[POWERPC] 83xx: Fix typo in mpc837x compatible entries
[POWERPC] 85xx: convert sbc85* boards to use machine_device_initcall
[POWERPC] 83xx: rework platform Kconfig
[POWERPC] 85xx: rework platform Kconfig
[POWERPC] 86xx: Remove unused IRQ defines
[POWERPC] QE: Explicitly set address-cells and size cells for muram
[POWERPC] Convert StorCenter DTS file to /dts-v1/ format.
[POWERPC] 86xx: Convert all 86xx DTS files to /dts-v1/ format.
[PPC] Remove 85xx from arch/ppc
[PPC] Remove 83xx from arch/ppc
...
Diffstat (limited to 'include')
68 files changed, 1059 insertions, 1229 deletions
diff --git a/include/asm-powerpc/8xx_immap.h b/include/asm-powerpc/8xx_immap.h index 1311cefdfd30..4b0e15206006 100644 --- a/include/asm-powerpc/8xx_immap.h +++ b/include/asm-powerpc/8xx_immap.h @@ -123,7 +123,7 @@ typedef struct mem_ctlr { #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ #define OR_BI 0x00000100 /* Burst inhibit */ -#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ +#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h index 48df9f330e76..77e39dad9728 100644 --- a/include/asm-powerpc/cpm.h +++ b/include/asm-powerpc/cpm.h @@ -4,11 +4,85 @@ #include <linux/compiler.h> #include <linux/types.h> +/* Buffer descriptors used by many of the CPM protocols. */ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +/* Buffer descriptor control/status used by serial + */ + +#define BD_SC_EMPTY (0x8000) /* Receive is empty */ +#define BD_SC_READY (0x8000) /* Transmit is ready */ +#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ +#define BD_SC_LAST (0x0800) /* Last buffer in frame */ +#define BD_SC_TC (0x0400) /* Transmit CRC */ +#define BD_SC_CM (0x0200) /* Continous mode */ +#define BD_SC_ID (0x0100) /* Rec'd too many idles */ +#define BD_SC_P (0x0100) /* xmt preamble */ +#define BD_SC_BR (0x0020) /* Break received */ +#define BD_SC_FR (0x0010) /* Framing error */ +#define BD_SC_PR (0x0008) /* Parity error */ +#define BD_SC_NAK (0x0004) /* NAK - did not respond */ +#define BD_SC_OV (0x0002) /* Overrun */ +#define BD_SC_UN (0x0002) /* Underrun */ +#define BD_SC_CD (0x0001) /* */ +#define BD_SC_CL (0x0001) /* Collision */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY (0x8000) +#define BD_ENET_RX_WRAP (0x2000) +#define BD_ENET_RX_INTR (0x1000) +#define BD_ENET_RX_LAST (0x0800) +#define BD_ENET_RX_FIRST (0x0400) +#define BD_ENET_RX_MISS (0x0100) +#define BD_ENET_RX_BC (0x0080) /* FCC Only */ +#define BD_ENET_RX_MC (0x0040) /* FCC Only */ +#define BD_ENET_RX_LG (0x0020) +#define BD_ENET_RX_NO (0x0010) +#define BD_ENET_RX_SH (0x0008) +#define BD_ENET_RX_CR (0x0004) +#define BD_ENET_RX_OV (0x0002) +#define BD_ENET_RX_CL (0x0001) +#define BD_ENET_RX_STATS (0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY (0x8000) +#define BD_ENET_TX_PAD (0x4000) +#define BD_ENET_TX_WRAP (0x2000) +#define BD_ENET_TX_INTR (0x1000) +#define BD_ENET_TX_LAST (0x0800) +#define BD_ENET_TX_TC (0x0400) +#define BD_ENET_TX_DEF (0x0200) +#define BD_ENET_TX_HB (0x0100) +#define BD_ENET_TX_LC (0x0080) +#define BD_ENET_TX_RL (0x0040) +#define BD_ENET_TX_RCMASK (0x003c) +#define BD_ENET_TX_UN (0x0002) +#define BD_ENET_TX_CSL (0x0001) +#define BD_ENET_TX_STATS (0x03ff) /* All status bits */ + +/* Buffer descriptor control/status used by Transparent mode SCC. + */ +#define BD_SCC_TX_LAST (0x0800) + +/* Buffer descriptor control/status used by I2C. + */ +#define BD_I2C_START (0x0400) + int cpm_muram_init(void); unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); void __iomem *cpm_muram_addr(unsigned long offset); dma_addr_t cpm_muram_dma(void __iomem *addr); +int cpm_command(u32 command, u8 opcode); #endif diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/cpm1.h index 2ee59d7b335c..b2ebd6ac6dae 100644 --- a/include/asm-powerpc/commproc.h +++ b/include/asm-powerpc/cpm1.h @@ -14,8 +14,8 @@ * IDMA1 space. The remaining DP RAM is available for buffer descriptors * or other use. */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ +#ifndef __CPM1__ +#define __CPM1__ #include <asm/8xx_immap.h> #include <asm/ptrace.h> @@ -82,42 +82,14 @@ extern int cpm_dpfree(unsigned long offset); extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8* addr); +extern uint cpm_dpram_phys(u8 *addr); #endif extern void cpm_setbrg(uint brg, uint rate); -extern uint m8xx_cpm_hostalloc(uint size); -extern int m8xx_cpm_hostfree(uint start); -extern void m8xx_cpm_hostdump(void); - extern void cpm_load_patch(cpm8xx_t *cp); -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ -#define BD_SC_CL ((ushort)0x0001) /* Collision */ +extern void cpm_reset(void); /* Parameter RAM offsets. */ @@ -448,41 +420,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -551,8 +488,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* IIC parameter RAM. */ typedef struct iic { @@ -576,8 +511,6 @@ typedef struct iic { char res2[2]; /* Reserved */ } iic_t; -#define BD_IIC_START ((ushort)0x0400) - /* SPI parameter RAM. */ typedef struct spi { @@ -693,7 +626,7 @@ typedef struct risc_timer_pram { #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ #define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ @@ -749,4 +682,4 @@ enum cpm_clk { int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); -#endif /* __CPM_8XX__ */ +#endif /* __CPM1__ */ diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h index f1112c15ef96..b93a53eb55c1 100644 --- a/include/asm-powerpc/cpm2.h +++ b/include/asm-powerpc/cpm2.h @@ -132,29 +132,6 @@ extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); extern void cpm2_reset(void); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - /* Function code bits, usually generic to devices. */ #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ @@ -456,43 +433,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -562,8 +502,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) @@ -769,8 +707,6 @@ typedef struct spi { #define SPI_EB ((u_char)0x10) /* big endian byte order */ -#define BD_IIC_START ((ushort)0x0400) - /* IDMA parameter RAM */ typedef struct idma { diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index 4525c784dfd0..528ef183c221 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -57,6 +57,14 @@ enum powerpc_pmc_type { PPC_PMC_PA6T = 2, }; +struct pt_regs; + +extern int machine_check_generic(struct pt_regs *regs); +extern int machine_check_4xx(struct pt_regs *regs); +extern int machine_check_440A(struct pt_regs *regs); +extern int machine_check_e500(struct pt_regs *regs); +extern int machine_check_e200(struct pt_regs *regs); + /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ struct cpu_spec { /* CPU is matched via (PVR & pvr_mask) == pvr_value */ @@ -97,6 +105,11 @@ struct cpu_spec { /* Name of processor class, for the ELF AT_PLATFORM entry */ char *platform; + + /* Processor specific machine check handling. Return negative + * if the error is fatal, 1 if it was fully recovered and 0 to + * pass up (not CPU originated) */ + int (*machine_check)(struct pt_regs *regs); }; extern struct cpu_spec *cur_cpu_spec; diff --git a/include/asm-powerpc/cputhreads.h b/include/asm-powerpc/cputhreads.h new file mode 100644 index 000000000000..8485c28b5f47 --- /dev/null +++ b/include/asm-powerpc/cputhreads.h @@ -0,0 +1,71 @@ +#ifndef _ASM_POWERPC_CPUTHREADS_H +#define _ASM_POWERPC_CPUTHREADS_H + +#include <linux/cpumask.h> + +/* + * Mapping of threads to cores + */ + +#ifdef CONFIG_SMP +extern int threads_per_core; +extern int threads_shift; +extern cpumask_t threads_core_mask; +#else +#define threads_per_core 1 +#define threads_shift 0 +#define threads_core_mask (CPU_MASK_CPU0) +#endif + +/* cpu_thread_mask_to_cores - Return a cpumask of one per cores + * hit by the argument + * + * @threads: a cpumask of threads + * + * This function returns a cpumask which will have one "cpu" (or thread) + * bit set for each core that has at least one thread set in the argument. + * + * This can typically be used for things like IPI for tlb invalidations + * since those need to be done only once per core/TLB + */ +static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads) +{ + cpumask_t tmp, res; + int i; + + res = CPU_MASK_NONE; + for (i = 0; i < NR_CPUS; i += threads_per_core) { + cpus_shift_right(tmp, threads_core_mask, i); + if (cpus_intersects(threads, tmp)) + cpu_set(i, res); + } + return res; +} + +static inline int cpu_nr_cores(void) +{ + return NR_CPUS >> threads_shift; +} + +static inline cpumask_t cpu_online_cores_map(void) +{ + return cpu_thread_mask_to_cores(cpu_online_map); +} + +static inline int cpu_thread_to_core(int cpu) +{ + return cpu >> threads_shift; +} + +static inline int cpu_thread_in_core(int cpu) +{ + return cpu & (threads_per_core - 1); +} + +static inline int cpu_first_thread_in_core(int cpu) +{ + return cpu & ~(threads_per_core - 1); +} + +#endif /* _ASM_POWERPC_CPUTHREADS_H */ + diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index 8dbb1ab0aa04..af5fb31af559 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h @@ -22,6 +22,8 @@ #ifdef __KERNEL__ #ifndef __ASSEMBLY__ +#include <linux/spinlock.h> + typedef struct { unsigned int base; } dcr_host_t; @@ -55,20 +57,28 @@ do { \ } while (0) /* R/W of indirect DCRs make use of standard naming conventions for DCRs */ -#define mfdcri(base, reg) \ -({ \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mfdcr(base ## _CFGDATA); \ +extern spinlock_t dcr_ind_lock; + +#define mfdcri(base, reg) \ +({ \ + unsigned long flags; \ + unsigned int val; \ + spin_lock_irqsave(&dcr_ind_lock, flags); \ + mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ + val = mfdcr(DCRN_ ## base ## _CONFIG_DATA); \ + spin_unlock_irqrestore(&dcr_ind_lock, flags); \ + val; \ }) -#define mtdcri(base, reg, data) \ -do { \ - mtdcr(base ## _CFGADDR, base ## _ ## reg); \ - mtdcr(base ## _CFGDATA, data); \ +#define mtdcri(base, reg, data) \ +do { \ + unsigned long flags; \ + spin_lock_irqsave(&dcr_ind_lock, flags); \ + mtdcr(DCRN_ ## base ## _CONFIG_ADDR, reg); \ + mtdcr(DCRN_ ## base ## _CONFIG_DATA, data); \ + spin_unlock_irqrestore(&dcr_ind_lock, flags); \ } while (0) #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_DCR_NATIVE_H */ - - diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h new file mode 100644 index 000000000000..9f1fb98fcdc6 --- /dev/null +++ b/include/asm-powerpc/dcr-regs.h @@ -0,0 +1,71 @@ +/* + * Common DCR / SDR / CPR register definitions used on various IBM/AMCC + * 4xx processors + * + * Copyright 2007 Benjamin Herrenschmidt, IBM Corp + * <benh@kernel.crashing.org> + * + * Mostly lifted from asm-ppc/ibm4xx.h by + * + * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> + * + */ + +#ifndef __DCR_REGS_H__ +#define __DCR_REGS_H__ + +/* + * Most DCRs used for controlling devices such as the MAL, DMA engine, + * etc... are obtained for the device tree. + * + * The definitions in this files are fixed DCRs and indirect DCRs that + * are commonly used outside of specific drivers or refer to core + * common registers that may occasionally have to be tweaked outside + * of the driver main register set + */ + +/* CPRs (440GX and 440SP/440SPe) */ +#define DCRN_CPR0_CONFIG_ADDR 0xc +#define DCRN_CPR0_CONFIG_DATA 0xd + +/* SDRs (440GX and 440SP/440SPe) */ +#define DCRN_SDR0_CONFIG_ADDR 0xe +#define DCRN_SDR0_CONFIG_DATA 0xf + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_EPS 0x1c00000 +#define SDR0_PFC1_EPS_SHIFT 22 +#define SDR0_PFC1_RMII 0x02000000 +#define SDR0_MFR 0x4300 +#define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ +#define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ +#define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ +#define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */ +#define SDR0_MFR_T0TXFL 0x00080000 +#define SDR0_MFR_T0TXFH 0x00040000 +#define SDR0_MFR_T1TXFL 0x00020000 +#define SDR0_MFR_T1TXFH 0x00010000 +#define SDR0_MFR_E0TXFL 0x00008000 +#define SDR0_MFR_E0TXFH 0x00004000 +#define SDR0_MFR_E0RXFL 0x00002000 +#define SDR0_MFR_E0RXFH 0x00001000 +#define SDR0_MFR_E1TXFL 0x00000800 +#define SDR0_MFR_E1TXFH 0x00000400 +#define SDR0_MFR_E1RXFL 0x00000200 +#define SDR0_MFR_E1RXFH 0x00000100 +#define SDR0_MFR_E2TXFL 0x00000080 +#define SDR0_MFR_E2TXFH 0x00000040 +#define SDR0_MFR_E2RXFL 0x00000020 +#define SDR0_MFR_E2RXFH 0x00000010 +#define SDR0_MFR_E3TXFL 0x00000008 +#define SDR0_MFR_E3TXFH 0x00000004 +#define SDR0_MFR_E3RXFL 0x00000002 +#define SDR0_MFR_E3RXFH 0x00000001 +#define SDR0_UART0 0x0120 +#define SDR0_UART1 0x0121 +#define SDR0_UART2 0x0122 +#define SDR0_UART3 0x0123 +#define SDR0_CUST0 0x4000 + +#endif /* __DCR_REGS_H__ */ diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h index ff52013c0e2d..bbefb69bfb67 100644 --- a/include/asm-powerpc/dma-mapping.h +++ b/include/asm-powerpc/dma-mapping.h @@ -76,6 +76,11 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev) return dev->archdata.dma_ops; } +static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops) +{ + dev->archdata.dma_ops = ops; +} + static inline int dma_supported(struct device *dev, u64 mask) { struct dma_mapping_ops *dma_ops = get_dma_ops(dev); @@ -87,6 +92,9 @@ static inline int dma_supported(struct device *dev, u64 mask) return dma_ops->dma_supported(dev, mask); } +/* We have our own implementation of pci_set_dma_mask() */ +#define HAVE_ARCH_PCI_SET_DMA_MASK + static inline int dma_set_mask(struct device *dev, u64 dma_mask) { struct dma_mapping_ops *dma_ops = get_dma_ops(dev); @@ -186,8 +194,6 @@ static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, extern struct dma_mapping_ops dma_iommu_ops; extern struct dma_mapping_ops dma_direct_ops; -extern unsigned long dma_direct_offset; - #else /* CONFIG_PPC64 */ #define dma_supported(dev, mask) (1) diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h index 3671c128f271..1e41bd1c8502 100644 --- a/include/asm-powerpc/firmware.h +++ b/include/asm-powerpc/firmware.h @@ -64,7 +64,7 @@ enum { FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT, - FW_FEATURE_CELLEB_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_BEAT, + FW_FEATURE_CELLEB_ALWAYS = 0, FW_FEATURE_NATIVE_POSSIBLE = 0, FW_FEATURE_NATIVE_ALWAYS = 0, FW_FEATURE_POSSIBLE = diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h index 0ad4e653d464..0f165e59c326 100644 --- a/include/asm-powerpc/immap_86xx.h +++ b/include/asm-powerpc/immap_86xx.h @@ -89,14 +89,14 @@ struct ccsr_guts { * them. * * guts: Pointer to GUTS structure - * co: The DMA controller (1 or 2) + * co: The DMA controller (0 or 1) * ch: The channel on the DMA controller (0, 1, 2, or 3) * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) */ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, unsigned int co, unsigned int ch, unsigned int device) { - unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); + unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); } @@ -118,6 +118,27 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 +/* + * Set the DMA external control bits in the GUTS + * + * The DMA external control bits in the PMUXCR are only meaningful for + * channels 0 and 3. Any other channels are ignored. + * + * guts: Pointer to GUTS structure + * co: The DMA controller (0 or 1) + * ch: The channel on the DMA controller (0, 1, 2, or 3) + * value: the new value for the bit (0 or 1) + */ +static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, + unsigned int co, unsigned int ch, unsigned int value) +{ + if ((ch == 0) || (ch == 3)) { + unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; + + clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); + } +} + #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h index aba9806b31c9..82a452615097 100644 --- a/include/asm-powerpc/immap_qe.h +++ b/include/asm-powerpc/immap_qe.h @@ -393,9 +393,39 @@ struct dbg { u8 res2[0x48]; } __attribute__ ((packed)); -/* RISC Special Registers (Trap and Breakpoint) */ +/* + * RISC Special Registers (Trap and Breakpoint). These are described in + * the QE Developer's Handbook. + */ struct rsp { - u32 reg[0x40]; /* 64 32-bit registers */ + __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ + u8 res0[64]; + __be32 ibcr0; + __be32 ibs0; + __be32 ibcnr0; + u8 res1[4]; + __be32 ibcr1; + __be32 ibs1; + __be32 ibcnr1; + __be32 npcr; + __be32 dbcr; + __be32 dbar; + __be32 dbamr; + __be32 dbsr; + __be32 dbcnr; + u8 res2[12]; + __be32 dbdr_h; + __be32 dbdr_l; + __be32 dbdmr_h; + __be32 dbdmr_l; + __be32 bsr; + __be32 bor; + __be32 bior; + u8 res3[4]; + __be32 iatr[4]; + __be32 eccr; /* Exception control configuration register */ + __be32 eicr; + u8 res4[0x100-0xf8]; } __attribute__ ((packed)); struct qe_immap { diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h index e44cdfc8493a..7be26f615755 100644 --- a/include/asm-powerpc/io.h +++ b/include/asm-powerpc/io.h @@ -50,15 +50,16 @@ extern int check_legacy_ioport(unsigned long base_port); #define PCI_DRAM_OFFSET pci_dram_offset #else #define _IO_BASE pci_io_base -#define _ISA_MEM_BASE 0 +#define _ISA_MEM_BASE isa_mem_base #define PCI_DRAM_OFFSET 0 #endif extern unsigned long isa_io_base; -extern unsigned long isa_mem_base; extern unsigned long pci_io_base; extern unsigned long pci_dram_offset; +extern resource_size_t isa_mem_base; + #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits #endif diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h index 4a82fdccee92..7a3cef785abd 100644 --- a/include/asm-powerpc/iommu.h +++ b/include/asm-powerpc/iommu.h @@ -69,10 +69,9 @@ struct iommu_table { }; struct scatterlist; -struct device_node; /* Frees table for an individual device node */ -extern void iommu_free_table(struct device_node *dn); +extern void iommu_free_table(struct iommu_table *tbl, const char *node_name); /* Initializes an iommu_table based in values set in the passed-in * structure diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h index edec79dcb7c1..8ff08be00146 100644 --- a/include/asm-powerpc/ipic.h +++ b/include/asm-powerpc/ipic.h @@ -20,11 +20,13 @@ /* Flags when we init the IPIC */ #define IPIC_SPREADMODE_GRP_A 0x00000001 -#define IPIC_SPREADMODE_GRP_D 0x00000002 -#define IPIC_SPREADMODE_MIX_A 0x00000004 -#define IPIC_SPREADMODE_MIX_B 0x00000008 -#define IPIC_DISABLE_MCP_OUT 0x00000010 -#define IPIC_IRQ0_MCP 0x00000020 +#define IPIC_SPREADMODE_GRP_B 0x00000002 +#define IPIC_SPREADMODE_GRP_C 0x00000004 +#define IPIC_SPREADMODE_GRP_D 0x00000008 +#define IPIC_SPREADMODE_MIX_A 0x00000010 +#define IPIC_SPREADMODE_MIX_B 0x00000020 +#define IPIC_DISABLE_MCP_OUT 0x00000040 +#define IPIC_IRQ0_MCP 0x00000080 /* IPIC registers offsets */ #define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 1392db456523..b5c03127a9b9 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -483,218 +483,6 @@ static __inline__ int irq_canonicalize(int irq) */ #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> - -#define NR_IRQS (NR_IPIC_INTS) - -#elif defined(CONFIG_85xx) -/* Now include the board configuration specific associations. -*/ -#include <asm/mpc85xx.h> - -/* The MPC8548 openpic has 48 internal interrupts and 12 external - * interrupts. - * - * We are "flattening" the interrupt vectors of the cascaded CPM - * so that we can uniquely identify any interrupt source with a - * single integer. - */ -#define NR_CPM_INTS 64 -#define NR_EPIC_INTS 60 -#ifndef NR_8259_INTS -#define NR_8259_INTS 0 -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef CPM_IRQ_OFFSET -#define CPM_IRQ_OFFSET 0 -#endif - -#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) - -/* Internal IRQs on MPC85xx OpenPIC */ - -#ifndef MPC85xx_OPENPIC_IRQ_OFFSET -#ifdef CONFIG_CPM2 -#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) -#else -#define MPC85xx_OPENPIC_IRQ_OFFSET 0 -#endif -#endif - -/* Not all of these exist on all MPC85xx implementations */ -#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* CPM related interrupts */ -#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) -#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) -#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) -#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) -#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) -#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) -#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) -#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) -#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) -#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) -#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) -#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) -#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) -#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) -#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) -#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) -#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) -#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) -#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) -#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) -#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) -#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) -#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) -#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) -#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) -#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) -#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) -#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) -#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) -#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) -#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) -#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) - -#elif defined(CONFIG_PPC_86xx) -#include <asm/mpc86xx.h> - -#define NR_EPIC_INTS 48 -#ifndef NR_8259_INTS -#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */ -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef I8259_OFFSET -#define I8259_OFFSET 0 -#endif - -#define NR_IRQS 256 - -/* Internal IRQs on MPC86xx OpenPIC */ - -#ifndef MPC86xx_OPENPIC_IRQ_OFFSET -#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS -#endif - -/* The 48 internal sources */ -#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* no 10,11 */ -#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 25 */ -#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 29,30,31 */ -#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 35,36 */ -#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC86xx_IRQ_EXT_BASE 48 -#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) - #else /* CONFIG_40x + CONFIG_8xx */ /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) diff --git a/include/asm-powerpc/iseries/hv_lp_event.h b/include/asm-powerpc/iseries/hv_lp_event.h index 6ce2ce1e2690..8f5da7d77202 100644 --- a/include/asm-powerpc/iseries/hv_lp_event.h +++ b/include/asm-powerpc/iseries/hv_lp_event.h @@ -78,7 +78,7 @@ extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex); /* * Close an Lp Event Path for a type and partition - * returns 0 on sucess + * returns 0 on success */ extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex); diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h index b6f817b8ba3d..701857bc8e24 100644 --- a/include/asm-powerpc/kexec.h +++ b/include/asm-powerpc/kexec.h @@ -123,6 +123,9 @@ struct pt_regs; extern void default_machine_kexec(struct kimage *image); extern int default_machine_kexec_prepare(struct kimage *image); extern void default_machine_crash_shutdown(struct pt_regs *regs); +typedef void (*crash_shutdown_t)(void); +extern int crash_shutdown_register(crash_shutdown_t handler); +extern int crash_shutdown_unregister(crash_shutdown_t handler); extern void machine_kexec_simple(struct kimage *image); extern void crash_kexec_secondary(struct pt_regs *regs); diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h index b5f9f4c9c294..5d1dc48a0bb8 100644 --- a/include/asm-powerpc/lmb.h +++ b/include/asm-powerpc/lmb.h @@ -51,6 +51,7 @@ extern unsigned long __init __lmb_alloc_base(unsigned long size, extern unsigned long __init lmb_phys_mem_size(void); extern unsigned long __init lmb_end_of_DRAM(void); extern void __init lmb_enforce_memory_limit(unsigned long memory_limit); +extern int __init lmb_is_reserved(unsigned long addr); extern void lmb_dump_all(void); diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h index 6968f4300dca..0872ec228c1e 100644 --- a/include/asm-powerpc/machdep.h +++ b/include/asm-powerpc/machdep.h @@ -204,6 +204,13 @@ struct machdep_calls { /* * optional PCI "hooks" */ + /* Called in indirect_* to avoid touching devices */ + int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char); + + /* Called at then very end of pcibios_init() */ + void (*pcibios_after_init)(void); + +#endif /* CONFIG_PPC32 */ /* Called after PPC generic resource fixup to perform machine specific fixups */ @@ -212,18 +219,9 @@ struct machdep_calls { /* Called for each PCI bus in the system when it's probed */ void (*pcibios_fixup_bus)(struct pci_bus *); - /* Called when pci_enable_device() is called (initial=0) or - * when a device with no assigned resource is found (initial=1). - * Returns 0 to allow assignment/enabling of the device. */ - int (*pcibios_enable_device_hook)(struct pci_dev *, int initial); - - /* Called in indirect_* to avoid touching devices */ - int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char); - - /* Called at then very end of pcibios_init() */ - void (*pcibios_after_init)(void); - -#endif /* CONFIG_PPC32 */ + /* Called when pci_enable_device() is called. Returns 0 to + * allow assignment/enabling of the device. */ + int (*pcibios_enable_device_hook)(struct pci_dev *); /* Called to shutdown machine specific hardware not already controlled * by other drivers. @@ -253,6 +251,16 @@ struct machdep_calls { */ void (*machine_kexec)(struct kimage *image); #endif /* CONFIG_KEXEC */ + +#ifdef CONFIG_SUSPEND + /* These are called to disable and enable, respectively, IRQs when + * entering a suspend state. If NULL, then the generic versions + * will be called. The generic versions disable/enable the + * decrementer along with interrupts. + */ + void (*suspend_disable_irqs)(void); + void (*suspend_enable_irqs)(void); +#endif }; extern void power4_idle(void); @@ -326,5 +334,31 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal) ppc_md.log_error(buf, err_type, fatal); } +#define __define_machine_initcall(mach,level,fn,id) \ + static int __init __machine_initcall_##mach##_##fn(void) { \ + if (machine_is(mach)) return fn(); \ + return 0; \ + } \ + __define_initcall(level,__machine_initcall_##mach##_##fn,id); + +#define machine_core_initcall(mach,fn) __define_machine_initcall(mach,"1",fn,1) +#define machine_core_initcall_sync(mach,fn) __define_machine_initcall(mach,"1s",fn,1s) +#define machine_postcore_initcall(mach,fn) __define_machine_initcall(mach,"2",fn,2) +#define machine_postcore_initcall_sync(mach,fn) __define_machine_initcall(mach,"2s",fn,2s) +#define machine_arch_initcall(mach,fn) __define_machine_initcall(mach,"3",fn,3) +#define machine_arch_initcall_sync(mach,fn) __define_machine_initcall(mach,"3s",fn,3s) +#define machine_subsys_initcall(mach,fn) __define_machine_initcall(mach,"4",fn,4) +#define machine_subsys_initcall_sync(mach,fn) __define_machine_initcall(mach,"4s",fn,4s) +#define machine_fs_initcall(mach,fn) __define_machine_initcall(mach,"5",fn,5) +#define machine_fs_initcall_sync(mach,fn) __define_machine_initcall(mach,"5s",fn,5s) +#define machine_rootfs_initcall(mach,fn) __define_machine_initcall(mach,"rootfs",fn,rootfs) +#define machine_device_initcall(mach,fn) __define_machine_initcall(mach,"6",fn,6) +#define machine_device_initcall_sync(mach,fn) __define_machine_initcall(mach,"6s",fn,6s) +#define machine_late_initcall(mach,fn) __define_machine_initcall(mach,"7",fn,7) +#define machine_late_initcall_sync(mach,fn) __define_machine_initcall(mach,"7s",fn,7s) + +void generic_suspend_disable_irqs(void); +void generic_suspend_enable_irqs(void); + #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_MACHDEP_H */ diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index 82328dec2b52..2864fa3989ea 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -80,7 +80,7 @@ extern char initial_stab[]; #define HPTE_V_AVPN_SHIFT 7 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) -#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80)) +#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) @@ -180,6 +180,7 @@ extern int mmu_vmalloc_psize; extern int mmu_io_psize; extern int mmu_kernel_ssize; extern int mmu_highuser_ssize; +extern u16 mmu_slb_size; /* * If the processor supports 64k normal pages but not 64k cache @@ -264,7 +265,7 @@ static inline unsigned long hpt_hash(unsigned long va, unsigned int shift, extern int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid, pte_t *ptep, unsigned long trap, - unsigned int local, int ssize); + unsigned int local, int ssize, int subpage_prot); extern int __hash_page_64K(unsigned long ea, unsigned long access, unsigned long vsid, pte_t *ptep, unsigned long trap, unsigned int local, int ssize); @@ -277,6 +278,8 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access, extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, unsigned long pstart, unsigned long mode, int psize, int ssize); +extern void set_huge_psize(int psize); +extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); extern void htab_initialize(void); extern void htab_initialize_secondary(void); diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h index fcb2ebbfddbc..81ef10b6b672 100644 --- a/include/asm-powerpc/mpc52xx.h +++ b/include/asm-powerpc/mpc52xx.h @@ -248,19 +248,25 @@ struct mpc52xx_cdm { #ifndef __ASSEMBLY__ -extern void __iomem * mpc52xx_find_and_map(const char *); -extern void __iomem * mpc52xx_find_and_map_path(const char *path); +/* mpc52xx_common.c */ extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node); extern void mpc5200_setup_xlb_arbiter(void); extern void mpc52xx_declare_of_platform_devices(void); +extern void mpc52xx_map_common_devices(void); +extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv); +extern void mpc52xx_restart(char *cmd); +/* mpc52xx_pic.c */ extern void mpc52xx_init_irq(void); extern unsigned int mpc52xx_get_irq(void); +/* mpc52xx_pci.c */ +#ifdef CONFIG_PCI extern int __init mpc52xx_add_bridge(struct device_node *node); - -extern void __init mpc52xx_map_wdt(void); -extern void mpc52xx_restart(char *cmd); +extern void __init mpc52xx_setup_pci(void); +#else +static inline void mpc52xx_setup_pci(void) { } +#endif #endif /* __ASSEMBLY__ */ diff --git a/include/asm-powerpc/mpc52xx_psc.h b/include/asm-powerpc/mpc52xx_psc.h index 26690d2b32f5..bea42b95390f 100644 --- a/include/asm-powerpc/mpc52xx_psc.h +++ b/include/asm-powerpc/mpc52xx_psc.h @@ -153,6 +153,9 @@ struct mpc52xx_psc { u8 reserved16[3]; u8 irfdr; /* PSC + 0x54 */ u8 reserved17[3]; +}; + +struct mpc52xx_psc_fifo { u16 rfnum; /* PSC + 0x58 */ u16 reserved18; u16 tfnum; /* PSC + 0x5c */ diff --git a/include/asm-powerpc/mpc8260.h b/include/asm-powerpc/mpc8260.h index e0d480790e12..03317e1e6185 100644 --- a/include/asm-powerpc/mpc8260.h +++ b/include/asm-powerpc/mpc8260.h @@ -8,6 +8,7 @@ #ifndef __ASM_POWERPC_MPC8260_H__ #define __ASM_POWERPC_MPC8260_H__ +#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */ #ifdef CONFIG_8260 diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h index 2be014b6f57c..98f3c4f17328 100644 --- a/include/asm-powerpc/mpc8xx.h +++ b/include/asm-powerpc/mpc8xx.h @@ -4,29 +4,9 @@ * file that has to include MPC8xx configuration, they all include * this one and the configuration switching is done here. */ -#ifdef __KERNEL__ #ifndef __CONFIG_8xx_DEFS #define __CONFIG_8xx_DEFS - -#ifdef CONFIG_8xx - -#ifdef CONFIG_FADS -#include <platforms/fads.h> -#endif - -#if defined(CONFIG_MPC86XADS) -#include <platforms/8xx/mpc86xads.h> -#endif - -#if defined(CONFIG_MPC885ADS) -#include <platforms/8xx/mpc885ads.h> -#endif - -#ifdef CONFIG_PCMCIA_M8XX extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; -#endif -#endif /* CONFIG_8xx */ #endif /* __CONFIG_8xx_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index ae84dde3bc7f..943c5a3fac8a 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h @@ -22,7 +22,9 @@ #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 +#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff +#define MPIC_GREG_GCONF_MCK 0x08000000 #define MPIC_GREG_GLOBAL_CONF_1 0x00030 #define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 @@ -78,6 +80,7 @@ #define MPIC_CPU_WHOAMI_MASK 0x0000001f #define MPIC_CPU_INTACK 0x000a0 #define MPIC_CPU_EOI 0x000b0 +#define MPIC_CPU_MCACK 0x000c0 /* * Per-source registers @@ -141,6 +144,7 @@ #define TSI108_CPU_WHOAMI 0xffffffff #define TSI108_CPU_INTACK 0x00004 #define TSI108_CPU_EOI 0x00008 +#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ /* * Per-source registers @@ -183,6 +187,7 @@ enum { MPIC_IDX_CPU_WHOAMI, MPIC_IDX_CPU_INTACK, MPIC_IDX_CPU_EOI, + MPIC_IDX_CPU_MCACK, MPIC_IDX_IRQ_BASE, MPIC_IDX_IRQ_STRIDE, @@ -344,6 +349,10 @@ struct mpic #define MPIC_USES_DCR 0x00000080 /* MPIC has 11-bit vector fields (or larger) */ #define MPIC_LARGE_VECTORS 0x00000100 +/* Enable delivery of prio 15 interrupts as MCK instead of EE */ +#define MPIC_ENABLE_MCK 0x00000200 +/* Disable bias among target selection, spread interrupts evenly */ +#define MPIC_NO_BIAS 0x00000400 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 @@ -447,10 +456,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); /* Send a message (IPI) to a given target (cpu number or MSG_*) */ void smp_mpic_message_pass(int target, int msg); +/* Unmask a specific virq */ +extern void mpic_unmask_irq(unsigned int irq); +/* Mask a specific virq */ +extern void mpic_mask_irq(unsigned int irq); +/* EOI a specific virq */ +extern void mpic_end_irq(unsigned int irq); + /* Fetch interrupt from a given mpic */ extern unsigned int mpic_get_one_irq(struct mpic *mpic); -/* This one gets to the primary mpic */ +/* This one gets from the primary mpic */ extern unsigned int mpic_get_irq(void); +/* Fetch Machine Check interrupt from primary mpic */ +extern unsigned int mpic_get_mcirq(void); /* Set the EPIC clock ratio */ void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); diff --git a/include/asm-powerpc/nvram.h b/include/asm-powerpc/nvram.h index 9877982508bf..4e7059cc6113 100644 --- a/include/asm-powerpc/nvram.h +++ b/include/asm-powerpc/nvram.h @@ -10,6 +10,8 @@ #ifndef _ASM_POWERPC_NVRAM_H #define _ASM_POWERPC_NVRAM_H +#include <linux/errno.h> + #define NVRW_CNT 0x20 #define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */ #define NVRAM_BLOCK_LEN 16 @@ -71,7 +73,16 @@ extern int nvram_clear_error_log(void); extern struct nvram_partition *nvram_find_partition(int sig, const char *name); extern int pSeries_nvram_init(void); + +#ifdef CONFIG_MMIO_NVRAM extern int mmio_nvram_init(void); +#else +static inline int mmio_nvram_init(void) +{ + return -ENODEV; +} +#endif + #endif /* __KERNEL__ */ /* PowerMac specific nvram stuffs */ diff --git a/include/asm-powerpc/of_platform.h b/include/asm-powerpc/of_platform.h index 80e6fad28b4f..18659ef72139 100644 --- a/include/asm-powerpc/of_platform.h +++ b/include/asm-powerpc/of_platform.h @@ -15,8 +15,14 @@ #include <linux/of_platform.h> /* Platform drivers register/unregister */ -extern int of_register_platform_driver(struct of_platform_driver *drv); -extern void of_unregister_platform_driver(struct of_platform_driver *drv); +static inline int of_register_platform_driver(struct of_platform_driver *drv) +{ + return of_register_driver(drv, &of_platform_bus_type); +} +static inline void of_unregister_platform_driver(struct of_platform_driver *drv) +{ + of_unregister_driver(drv); +} /* Platform devices and busses creation */ extern struct of_device *of_platform_device_create(struct device_node *np, @@ -26,9 +32,11 @@ extern struct of_device *of_platform_device_create(struct device_node *np, #define OF_NO_DEEP_PROBE ((struct of_device_id *)-1) extern int of_platform_bus_probe(struct device_node *root, - struct of_device_id *matches, + const struct of_device_id *matches, struct device *parent); extern struct of_device *of_find_device_by_phandle(phandle ph); +extern void of_instantiate_rtc(void); + #endif /* _ASM_POWERPC_OF_PLATFORM_H */ diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index d8bdc79db12e..e5802c62f428 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -1,15 +1,42 @@ #ifndef _ASM_POWERPC_PCI_BRIDGE_H #define _ASM_POWERPC_PCI_BRIDGE_H #ifdef __KERNEL__ - +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ #include <linux/pci.h> #include <linux/list.h> #include <linux/ioport.h> -#ifndef CONFIG_PPC64 - struct device_node; -struct pci_controller; + +extern unsigned int ppc_pci_flags; +enum { + /* Force re-assigning all resources (ignore firmware + * setup completely) + */ + PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, + + /* Re-assign all bus numbers */ + PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, + + /* Do not try to assign, just use existing setup */ + PPC_PCI_PROBE_ONLY = 0x00000004, + + /* Don't bother with ISA alignment unless the bridge has + * ISA forwarding enabled + */ + PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, + + /* Enable domain numbers in /proc */ + PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, + /* ... except for domain 0 */ + PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, +}; + /* * Structure of a PCI controller (host bridge) @@ -17,26 +44,41 @@ struct pci_controller; struct pci_controller { struct pci_bus *bus; char is_dynamic; - void *arch_data; +#ifdef CONFIG_PPC64 + int node; +#endif + struct device_node *dn; struct list_head list_node; struct device *parent; int first_busno; int last_busno; +#ifndef CONFIG_PPC64 int self_busno; +#endif void __iomem *io_base_virt; +#ifdef CONFIG_PPC64 + void *io_base_alloc; +#endif resource_size_t io_base_phys; +#ifndef CONFIG_PPC64 + resource_size_t pci_io_size; +#endif /* Some machines (PReP) have a non 1:1 mapping of * the PCI memory space in the CPU bus space */ resource_size_t pci_mem_offset; +#ifdef CONFIG_PPC64 + unsigned long pci_io_size; +#endif struct pci_ops *ops; - volatile unsigned int __iomem *cfg_addr; - volatile void __iomem *cfg_data; + unsigned int __iomem *cfg_addr; + void __iomem *cfg_data; +#ifndef CONFIG_PPC64 /* * Used for variants of PCI indirect handling and possible quirks: * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 @@ -51,21 +93,30 @@ struct pci_controller { * set. * BIG_ENDIAN - cfg_addr is a big endian register */ -#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) -#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) -#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) -#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) -#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) +#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 +#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 +#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 +#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 +#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 u32 indirect_type; - +#endif /* !CONFIG_PPC64 */ /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more */ struct resource io_resource; struct resource mem_resources[3]; int global_number; /* PCI domain number */ +#ifdef CONFIG_PPC64 + unsigned long buid; + unsigned long dma_window_base_cur; + unsigned long dma_window_size; + + void *private_data; +#endif /* CONFIG_PPC64 */ }; +#ifndef CONFIG_PPC64 + static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) { return bus->sysdata; @@ -81,18 +132,18 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) /* These are used for config access before all the PCI probing has been done. */ -int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 *val); -int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 *val); -int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 *val); -int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, - int where, u8 val); -int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, - int where, u16 val); -int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, - int where, u32 val); +extern int early_read_config_byte(struct pci_controller *hose, int bus, + int dev_fn, int where, u8 *val); +extern int early_read_config_word(struct pci_controller *hose, int bus, + int dev_fn, int where, u16 *val); +extern int early_read_config_dword(struct pci_controller *hose, int bus, + int dev_fn, int where, u32 *val); +extern int early_write_config_byte(struct pci_controller *hose, int bus, + int dev_fn, int where, u8 val); +extern int early_write_config_word(struct pci_controller *hose, int bus, + int dev_fn, int where, u16 val); +extern int early_write_config_dword(struct pci_controller *hose, int bus, + int dev_fn, int where, u32 val); extern int early_find_capability(struct pci_controller *hose, int bus, int dev_fn, int cap); @@ -101,87 +152,33 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); -extern void __init update_bridge_resource(struct pci_dev *dev, - struct resource *res); - -#else - - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* - * Structure of a PCI controller (host bridge) - */ -struct pci_controller { - struct pci_bus *bus; - char is_dynamic; - int node; - void *arch_data; - struct list_head list_node; - struct device *parent; - - int first_busno; - int last_busno; - - void __iomem *io_base_virt; - void *io_base_alloc; - resource_size_t io_base_phys; - - /* Some machines have a non 1:1 mapping of - * the PCI memory space in the CPU bus space - */ - resource_size_t pci_mem_offset; - unsigned long pci_io_size; - - struct pci_ops *ops; - volatile unsigned int __iomem *cfg_addr; - volatile void __iomem *cfg_data; - - /* Currently, we limit ourselves to 1 IO range and 3 mem - * ranges since the common pci_bus structure can't handle more - */ - struct resource io_resource; - struct resource mem_resources[3]; - int global_number; - unsigned long buid; - unsigned long dma_window_base_cur; - unsigned long dma_window_size; - - void *private_data; -}; +#else /* CONFIG_PPC64 */ /* * PCI stuff, for nodes representing PCI devices, pointed to * by device_node->data. */ -struct pci_controller; struct iommu_table; struct pci_dn { int busno; /* pci bus number */ - int bussubno; /* pci subordinate bus number */ int devfn; /* pci device and function number */ - int class_code; /* pci device class */ struct pci_controller *phb; /* for pci devices */ struct iommu_table *iommu_table; /* for phb's or bridges */ - struct pci_dev *pcidev; /* back-pointer to the pci device */ struct device_node *node; /* back-pointer to the device_node */ int pci_ext_config_space; /* for pci devices */ #ifdef CONFIG_EEH + struct pci_dev *pcidev; /* back-pointer to the pci device */ + int class_code; /* pci device class */ int eeh_mode; /* See eeh.h for possible EEH_MODEs */ int eeh_config_addr; int eeh_pe_config_addr; /* new-style partition endpoint address */ - int eeh_check_count; /* # times driver ignored error */ - int eeh_freeze_count; /* # times this device froze up. */ - int eeh_false_positives; /* # times this device reported #ff's */ + int eeh_check_count; /* # times driver ignored error */ + int eeh_freeze_count; /* # times this device froze up. */ + int eeh_false_positives; /* # times this device reported #ff's */ u32 config_space[16]; /* saved PCI config space */ #endif }; @@ -189,7 +186,7 @@ struct pci_dn { /* Get the pointer to a device_node's pci_dn */ #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) -struct device_node *fetch_dev_dn(struct pci_dev *dev); +extern struct device_node *fetch_dev_dn(struct pci_dev *dev); /* Get a device_node from a pci_dev. This code must be fast except * in the case where the sysdata is incorrect and needs to be fixed @@ -227,14 +224,14 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) } /** Find the bus corresponding to the indicated device node */ -struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); +extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); /** Remove all of the PCI devices under this bus */ -void pcibios_remove_pci_devices(struct pci_bus *bus); +extern void pcibios_remove_pci_devices(struct pci_bus *bus); /** Discover new pci devices under this bus, and add them */ -void pcibios_add_pci_devices(struct pci_bus * bus); -void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus); +extern void pcibios_add_pci_devices(struct pci_bus *bus); +extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus); extern int pcibios_remove_root_bus(struct pci_controller *phb); @@ -270,20 +267,18 @@ extern int pcibios_map_io_space(struct pci_bus *bus); #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) #endif -#endif /* CONFIG_PPC64 */ +#endif /* CONFIG_PPC64 */ /* Get the PCI host controller for an OF device */ -extern struct pci_controller* -pci_find_hose_for_OF_device(struct device_node* node); +extern struct pci_controller *pci_find_hose_for_OF_device( + struct device_node* node); /* Fill up host controller resources from the OF node */ -extern void -pci_process_bridge_OF_ranges(struct pci_controller *hose, - struct device_node *dev, int primary); +extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, + struct device_node *dev, int primary); /* Allocate & free a PCI host bridge structure */ -extern struct pci_controller * -pcibios_alloc_controller(struct device_node *dev); +extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); extern void pcibios_free_controller(struct pci_controller *phb); #ifdef CONFIG_PCI @@ -298,9 +293,7 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) { return 0; } -#endif - +#endif /* CONFIG_PCI */ - -#endif /* __KERNEL__ */ -#endif +#endif /* __KERNEL__ */ +#endif /* _ASM_POWERPC_PCI_BRIDGE_H */ diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h index 7b11765c6865..a05a942b1c25 100644 --- a/include/asm-powerpc/pci.h +++ b/include/asm-powerpc/pci.h @@ -36,11 +36,10 @@ struct pci_dev; /* * Set this to 1 if you want the kernel to re-assign all PCI - * bus numbers + * bus numbers (don't do that on ppc64 yet !) */ -extern int pci_assign_all_buses; -#define pcibios_assign_all_busses() (pci_assign_all_buses) - +#define pcibios_assign_all_busses() (ppc_pci_flags & \ + PPC_PCI_REASSIGN_ALL_BUS) #define pcibios_scan_all_fns(a, b) 0 static inline void pcibios_set_master(struct pci_dev *dev) @@ -95,9 +94,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, #define get_pci_dma_ops() NULL #endif -/* Decide whether to display the domain number in /proc */ -extern int pci_proc_domain(struct pci_bus *bus); - #else /* 32-bit */ #ifdef CONFIG_PCI @@ -109,17 +105,14 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, *strategy_parameter = ~0UL; } #endif - -/* Set the name of the bus as it appears in /proc/bus/pci */ -static inline int pci_proc_domain(struct pci_bus *bus) -{ - return 0; -} - #endif /* CONFIG_PPC64 */ extern int pci_domain_nr(struct pci_bus *bus); +/* Decide whether to display the domain number in /proc */ +extern int pci_proc_domain(struct pci_bus *bus); + + struct vm_area_struct; /* Map a range of PCI memory or I/O space for a device into user space */ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, @@ -199,13 +192,12 @@ static inline struct resource *pcibios_select_root(struct pci_dev *pdev, return root; } -extern void pcibios_fixup_device_resources(struct pci_dev *dev, - struct pci_bus *bus); - extern void pcibios_setup_new_device(struct pci_dev *dev); extern void pcibios_claim_one_bus(struct pci_bus *b); +extern void pcibios_resource_survey(void); + extern struct pci_controller *init_phb_dynamic(struct device_node *dn); extern struct pci_dev *of_create_pci_dev(struct device_node *node, @@ -229,5 +221,8 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar, const struct resource *rsrc, resource_size_t *start, resource_size_t *end); +extern void pcibios_do_bus_setup(struct pci_bus *bus); +extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus); + #endif /* __KERNEL__ */ #endif /* __ASM_POWERPC_PCI_H */ diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h index 94d0294341d6..43214c8085b7 100644 --- a/include/asm-powerpc/pgalloc-64.h +++ b/include/asm-powerpc/pgalloc-64.h @@ -12,6 +12,10 @@ #include <linux/cpumask.h> #include <linux/percpu.h> +#ifndef CONFIG_PPC_SUBPAGE_PROT +static inline void subpage_prot_free(pgd_t *pgd) {} +#endif + extern struct kmem_cache *pgtable_cache[]; #define PGD_CACHE_NUM 0 @@ -27,6 +31,7 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm) static inline void pgd_free(pgd_t *pgd) { + subpage_prot_free(pgd); kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd); } diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h index bd54b772fbc6..1cbd6b377eea 100644 --- a/include/asm-powerpc/pgtable-64k.h +++ b/include/asm-powerpc/pgtable-64k.h @@ -13,12 +13,49 @@ #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) -#endif /* __ASSEMBLY__ */ #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) +#ifdef CONFIG_PPC_SUBPAGE_PROT +/* + * For the sub-page protection option, we extend the PGD with one of + * these. Basically we have a 3-level tree, with the top level being + * the protptrs array. To optimize speed and memory consumption when + * only addresses < 4GB are being protected, pointers to the first + * four pages of sub-page protection words are stored in the low_prot + * array. + * Each page of sub-page protection words protects 1GB (4 bytes + * protects 64k). For the 3-level tree, each page of pointers then + * protects 8TB. + */ +struct subpage_prot_table { + unsigned long maxaddr; /* only addresses < this are protected */ + unsigned int **protptrs[2]; + unsigned int *low_prot[4]; +}; + +#undef PGD_TABLE_SIZE +#define PGD_TABLE_SIZE ((sizeof(pgd_t) << PGD_INDEX_SIZE) + \ + sizeof(struct subpage_prot_table)) + +#define SBP_L1_BITS (PAGE_SHIFT - 2) +#define SBP_L2_BITS (PAGE_SHIFT - 3) +#define SBP_L1_COUNT (1 << SBP_L1_BITS) +#define SBP_L2_COUNT (1 << SBP_L2_BITS) +#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) +#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) + +extern void subpage_prot_free(pgd_t *pgd); + +static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd) +{ + return (struct subpage_prot_table *)(pgd + PTRS_PER_PGD); +} +#endif /* CONFIG_PPC_SUBPAGE_PROT */ +#endif /* __ASSEMBLY__ */ + /* With 4k base page size, hugepage PTEs go at the PMD level */ #define MIN_HUGEPTE_SHIFT PAGE_SHIFT diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h index b847aa10074b..854ab713f56c 100644 --- a/include/asm-powerpc/ppc-pci.h +++ b/include/asm-powerpc/ppc-pci.h @@ -22,7 +22,6 @@ extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary); extern struct list_head hose_list; -extern int global_phb_number; extern void find_and_init_phbs(void); @@ -47,9 +46,6 @@ extern void init_pci_config_tokens (void); extern unsigned long get_phb_buid (struct device_node *); extern int rtas_setup_phb(struct pci_controller *phb); -/* From iSeries PCI */ -extern void iSeries_pcibios_init(void); - extern unsigned long pci_probe_only; /* ---- EEH internal-use-only related routines ---- */ diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h index 925e2d384bb3..78b7b0d494c0 100644 --- a/include/asm-powerpc/prom.h +++ b/include/asm-powerpc/prom.h @@ -202,6 +202,10 @@ static inline unsigned long of_read_ulong(const u32 *cell, int size) */ extern u64 of_translate_address(struct device_node *np, const u32 *addr); +/* Translate a DMA address from device space to CPU space */ +extern u64 of_translate_dma_address(struct device_node *dev, + const u32 *in_addr); + /* Extract an address from a device, returns the region size and * the address space flags too. The PCI version uses a BAR number * instead of an absolute index diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h index f577a16c6728..2b693673eff4 100644 --- a/include/asm-powerpc/ps3.h +++ b/include/asm-powerpc/ps3.h @@ -24,6 +24,7 @@ #include <linux/init.h> #include <linux/types.h> #include <linux/device.h> +#include "cell-pmu.h" union ps3_firmware_version { u64 raw; @@ -317,6 +318,7 @@ enum ps3_match_id { PS3_MATCH_ID_STOR_FLASH = 8, PS3_MATCH_ID_SOUND = 9, PS3_MATCH_ID_GRAPHICS = 10, + PS3_MATCH_ID_LPM = 11, }; #define PS3_MODULE_ALIAS_EHCI "ps3:1" @@ -329,11 +331,13 @@ enum ps3_match_id { #define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8" #define PS3_MODULE_ALIAS_SOUND "ps3:9" #define PS3_MODULE_ALIAS_GRAPHICS "ps3:10" +#define PS3_MODULE_ALIAS_LPM "ps3:11" enum ps3_system_bus_device_type { PS3_DEVICE_TYPE_IOC0 = 1, PS3_DEVICE_TYPE_SB, PS3_DEVICE_TYPE_VUART, + PS3_DEVICE_TYPE_LPM, }; /** @@ -344,12 +348,17 @@ struct ps3_system_bus_device { enum ps3_match_id match_id; enum ps3_system_bus_device_type dev_type; - unsigned int bus_id; /* SB */ - unsigned int dev_id; /* SB */ + u64 bus_id; /* SB */ + u64 dev_id; /* SB */ unsigned int interrupt_id; /* SB */ struct ps3_dma_region *d_region; /* SB, IOC0 */ struct ps3_mmio_region *m_region; /* SB, IOC0*/ unsigned int port_number; /* VUART */ + struct { /* LPM */ + u64 node_id; + u64 pu_id; + u64 rights; + } lpm; /* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */ struct device core; @@ -438,5 +447,66 @@ struct ps3_prealloc { extern struct ps3_prealloc ps3fb_videomemory; extern struct ps3_prealloc ps3flash_bounce_buffer; +/* logical performance monitor */ + +/** + * enum ps3_lpm_rights - Rigths granted by the system policy module. + * + * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm. + * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer. + */ + +enum ps3_lpm_rights { + PS3_LPM_RIGHTS_USE_LPM = 0x001, + PS3_LPM_RIGHTS_USE_TB = 0x100, +}; + +/** + * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use. + * + * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer. + * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have + * rights @PS3_LPM_RIGHTS_USE_TB. + */ + +enum ps3_lpm_tb_type { + PS3_LPM_TB_TYPE_NONE = 0, + PS3_LPM_TB_TYPE_INTERNAL = 1, +}; + +int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache, + u64 tb_cache_size); +int ps3_lpm_close(void); +int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count, + unsigned long *bytes_copied); +int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf, + unsigned long count, unsigned long *bytes_copied); +void ps3_set_bookmark(u64 bookmark); +void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id); +int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit, + u8 bus_word); + +u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr); +void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val); +u32 ps3_read_ctr(u32 cpu, u32 ctr); +void ps3_write_ctr(u32 cpu, u32 ctr, u32 val); + +u32 ps3_read_pm07_control(u32 cpu, u32 ctr); +void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val); +u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg); +void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); + +u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr); +void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size); + +void ps3_enable_pm(u32 cpu); +void ps3_disable_pm(u32 cpu); +void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask); +void ps3_disable_pm_interrupts(u32 cpu); + +u32 ps3_get_and_clear_pm_interrupts(u32 cpu); +void ps3_sync_irq(int node); +u32 ps3_get_hw_thread_id(int cpu); +u64 ps3_get_spe_id(void *arg); #endif diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h index 3063363f6799..ffc150f602b8 100644 --- a/include/asm-powerpc/ptrace.h +++ b/include/asm-powerpc/ptrace.h @@ -106,7 +106,8 @@ extern int ptrace_put_reg(struct task_struct *task, int regno, */ #define FULL_REGS(regs) (((regs)->trap & 1) == 0) #ifndef __powerpc64__ -#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) == 0) +#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) +#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) #endif /* ! __powerpc64__ */ #define TRAP(regs) ((regs)->trap & ~0xF) #ifdef __powerpc64__ diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index 0dabe46a29d2..430dc77b35fc 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -28,6 +28,52 @@ #define MEM_PART_SECONDARY 1 #define MEM_PART_MURAM 2 +/* Clocks and BRGs */ +enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +}; + /* Export QE common operations */ extern void qe_reset(void); extern int par_io_init(struct device_node *np); @@ -38,7 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val); /* QE internal API */ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); -void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); +enum qe_clock qe_clock_source(const char *source); +int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); unsigned long qe_muram_alloc(int size, int align); @@ -47,6 +94,58 @@ unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); void qe_muram_dump(void); void *qe_muram_addr(unsigned long offset); +/* Structure that defines QE firmware binary files. + * + * See Documentation/powerpc/qe-firmware.txt for a description of these + * fields. + */ +struct qe_firmware { + struct qe_header { + __be32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + __be16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + __be64 extended_modes; /* Extended modes */ + __be32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + __be32 traps[16]; /* Trap addresses, 0 == ignore */ + __be32 eccr; /* The value for the ECCR register */ + __be32 iram_offset; /* Offset into I-RAM for the code */ + __be32 count; /* Number of 32-bit words of the code */ + __be32 code_offset; /* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + +/* Upload a firmware to the QE */ +int qe_upload_firmware(const struct qe_firmware *firmware); + +/* Obtain information on the uploaded firmware */ +struct qe_firmware_info *qe_get_firmware_info(void); + /* Buffer descriptors */ struct qe_bd { __be16 status; @@ -129,52 +228,6 @@ enum comm_dir { COMM_DIR_RX_AND_TX = 3 }; -/* Clocks and BRGs */ -enum qe_clock { - QE_CLK_NONE = 0, - QE_BRG1, /* Baud Rate Generator 1 */ - QE_BRG2, /* Baud Rate Generator 2 */ - QE_BRG3, /* Baud Rate Generator 3 */ - QE_BRG4, /* Baud Rate Generator 4 */ - QE_BRG5, /* Baud Rate Generator 5 */ - QE_BRG6, /* Baud Rate Generator 6 */ - QE_BRG7, /* Baud Rate Generator 7 */ - QE_BRG8, /* Baud Rate Generator 8 */ - QE_BRG9, /* Baud Rate Generator 9 */ - QE_BRG10, /* Baud Rate Generator 10 */ - QE_BRG11, /* Baud Rate Generator 11 */ - QE_BRG12, /* Baud Rate Generator 12 */ - QE_BRG13, /* Baud Rate Generator 13 */ - QE_BRG14, /* Baud Rate Generator 14 */ - QE_BRG15, /* Baud Rate Generator 15 */ - QE_BRG16, /* Baud Rate Generator 16 */ - QE_CLK1, /* Clock 1 */ - QE_CLK2, /* Clock 2 */ - QE_CLK3, /* Clock 3 */ - QE_CLK4, /* Clock 4 */ - QE_CLK5, /* Clock 5 */ - QE_CLK6, /* Clock 6 */ - QE_CLK7, /* Clock 7 */ - QE_CLK8, /* Clock 8 */ - QE_CLK9, /* Clock 9 */ - QE_CLK10, /* Clock 10 */ - QE_CLK11, /* Clock 11 */ - QE_CLK12, /* Clock 12 */ - QE_CLK13, /* Clock 13 */ - QE_CLK14, /* Clock 14 */ - QE_CLK15, /* Clock 15 */ - QE_CLK16, /* Clock 16 */ - QE_CLK17, /* Clock 17 */ - QE_CLK18, /* Clock 18 */ - QE_CLK19, /* Clock 19 */ - QE_CLK20, /* Clock 20 */ - QE_CLK21, /* Clock 21 */ - QE_CLK22, /* Clock 22 */ - QE_CLK23, /* Clock 23 */ - QE_CLK24, /* Clock 24 */ - QE_CLK_DUMMY, -}; - /* QE CMXUCR Registers. * There are two UCCs represented in each of the four CMXUCR registers. * These values are for the UCC in the LSBs @@ -328,6 +381,15 @@ enum qe_clock { #define QE_SDEBCR_BA_MASK 0x01FFFFFF +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ + /* UPC */ #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index e775ff1ca413..2408a29507e5 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -553,6 +553,7 @@ #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ +#define SPRN_BKMK 1020 /* Cell Bookmark Register */ #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ @@ -691,12 +692,6 @@ #define PV_BE 0x0070 #define PV_PA6T 0x0090 -/* - * Number of entries in the SLB. If this ever changes we should handle - * it with a use a cpu feature fixup. - */ -#define SLB_NUM_ENTRIES 64 - /* Macros for setting and retrieving special purpose registers */ #ifndef __ASSEMBLY__ #define mfmsr() ({unsigned long rval; \ diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h index 8fdc2b47afb9..0405ef479814 100644 --- a/include/asm-powerpc/reg_booke.h +++ b/include/asm-powerpc/reg_booke.h @@ -123,16 +123,23 @@ #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_ATB 0x20E /* Alternate Time Base */ +#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ +#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ +#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ #define SPRN_MCSR 0x23C /* Machine Check Status Register */ #define SPRN_MCAR 0x23D /* Machine Check Address Register */ #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ +#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ +#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ @@ -140,15 +147,18 @@ #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27A /* Process ID Register 2 */ #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_EPR 0x2BE /* External Proxy Register */ #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ #define SPRN_MMUCR 0x3B2 /* MMU Control Register */ #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ +#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define SPRN_SLER 0x3BB /* Little-endian real mode */ @@ -159,6 +169,7 @@ #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ #define SPRN_SVR 0x3FF /* System Version Register */ @@ -207,7 +218,6 @@ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ /* Bit definitions for the MCSR. */ -#ifdef CONFIG_440A #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ @@ -217,7 +227,7 @@ #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#endif + #ifdef CONFIG_E500 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ @@ -293,7 +303,7 @@ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */ #define ESR_FP 0x01000000 /* Floating Point Operation */ #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ diff --git a/include/asm-powerpc/setjmp.h b/include/asm-powerpc/setjmp.h new file mode 100644 index 000000000000..279d03a1eec6 --- /dev/null +++ b/include/asm-powerpc/setjmp.h @@ -0,0 +1,18 @@ +/* + * Copyright © 2008 Michael Neuling IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ +#ifndef _ASM_POWERPC_SETJMP_H +#define _ASM_POWERPC_SETJMP_H + +#define JMP_BUF_LEN 23 + +extern long setjmp(long *); +extern void longjmp(long *, long); + +#endif /* _ASM_POWERPC_SETJMP_H */ diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h index e49f644ca63a..7ae2753da565 100644 --- a/include/asm-powerpc/smu.h +++ b/include/asm-powerpc/smu.h @@ -22,7 +22,7 @@ * Partition info commands * * These commands are used to retrieve the sdb-partition-XX datas from - * the SMU. The lenght is always 2. First byte is the subcommand code + * the SMU. The length is always 2. First byte is the subcommand code * and second byte is the partition ID. * * The reply is 6 bytes: @@ -173,12 +173,12 @@ * Power supply control * * The "sub" command is an ASCII string in the data, the - * data lenght is that of the string. + * data length is that of the string. * * The VSLEW command can be used to get or set the voltage slewing. - * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of + * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of * reply at data offset 6, 7 and 8. - * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is + * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is * used to set the voltage slewing point. The SMU replies with "DONE" * I yet have to figure out their exact meaning of those 3 bytes in * both cases. They seem to be: @@ -201,20 +201,90 @@ */ #define SMU_CMD_READ_ADC 0xd8 + /* Misc commands * * This command seem to be a grab bag of various things + * + * Parameters: + * 1: subcommand */ #define SMU_CMD_MISC_df_COMMAND 0xdf -#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */ + +/* + * Sets "system ready" status + * + * I did not yet understand how it exactly works or what it does. + * + * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used + * the same codebase for all OF versions. On PowerBooks, this command would + * enable the backlight. For the G5s, it only activates the front LED. However, + * don't take this for granted. + * + * Parameters: + * 2: status [0x00, 0x01 or 0x02] + */ +#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 + +/* + * Sets mode of power switch. + * + * What this actually does is not yet known. Maybe it enables some interrupt. + * + * Parameters: + * 2: enable power switch? [0x00 or 0x01] + * 3 (optional): enable nmi? [0x00 or 0x01] + * + * Returns: + * If parameter 2 is 0x00 and parameter 3 is not specified, returns wether + * NMI is enabled. Otherwise unknown. + */ #define SMU_CMD_MISC_df_NMI_OPTION 0x04 +/* Sets LED dimm offset. + * + * The front LED dimms itself during sleep. Its brightness (or, well, the PWM + * frequency) depends on current time. Therefore, the SMU needs to know the + * timezone. + * + * Parameters: + * 2-8: unknown (BCD coding) + */ +#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99 + + /* * Version info commands * - * I haven't quite tried to figure out how these work + * Parameters: + * 1 (optional): Specifies version part to retrieve + * + * Returns: + * Version value */ #define SMU_CMD_VERSION_COMMAND 0xea +#define SMU_VERSION_RUNNING 0x00 +#define SMU_VERSION_BASE 0x01 +#define SMU_VERSION_UPDATE 0x02 + + +/* + * Switches + * + * These are switches whose status seems to be known to the SMU. + * + * Parameters: + * none + * + * Result: + * Switch bits (ORed, see below) + */ +#define SMU_CMD_SWITCHES 0xdc + +/* Switches bits */ +#define SMU_SWITCH_CASE_CLOSED 0x01 +#define SMU_SWITCH_AC_POWER 0x04 +#define SMU_SWITCH_POWER_SWITCH 0x08 /* @@ -243,10 +313,64 @@ */ #define SMU_CMD_MISC_ee_COMMAND 0xee #define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02 -#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */ + +/* Retrieves currently used watts. + * + * Parameters: + * 1: 0x03 (Meaning unknown) + */ +#define SMU_CMD_MISC_ee_GET_WATTS 0x03 + +#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */ #define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */ +/* + * Power related commands + * + * Parameters: + * 1: subcommand + */ +#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f + +/* SMU_POWER_EVENTS subcommands */ +enum { + SMU_PWR_GET_POWERUP_EVENTS = 0x00, + SMU_PWR_SET_POWERUP_EVENTS = 0x01, + SMU_PWR_CLR_POWERUP_EVENTS = 0x02, + SMU_PWR_GET_WAKEUP_EVENTS = 0x03, + SMU_PWR_SET_WAKEUP_EVENTS = 0x04, + SMU_PWR_CLR_WAKEUP_EVENTS = 0x05, + + /* + * Get last shutdown cause + * + * Returns: + * 1 byte (signed char): Last shutdown cause. Exact meaning unknown. + */ + SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07, + + /* + * Sets or gets server ID. Meaning or use is unknown. + * + * Parameters: + * 2 (optional): Set server ID (1 byte) + * + * Returns: + * 1 byte (server ID?) + */ + SMU_PWR_SERVER_ID = 0x08, +}; + +/* Power events wakeup bits */ +enum { + SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */ + SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */ + SMU_PWR_WAKEUP_AC_CHANGE = 0x04, + SMU_PWR_WAKEUP_LID_OPEN = 0x08, + SMU_PWR_WAKEUP_RING = 0x10, +}; + /* * - Kernel side interface - @@ -564,13 +688,13 @@ struct smu_user_cmd_hdr __u8 cmd; /* SMU command byte */ __u8 pad[3]; /* padding */ - __u32 data_len; /* Lenght of data following */ + __u32 data_len; /* Length of data following */ }; struct smu_user_reply_hdr { __u32 status; /* Command status */ - __u32 reply_len; /* Lenght of data follwing */ + __u32 reply_len; /* Length of data follwing */ }; #endif /* _SMU_H */ diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h index 48ad807a0b8a..e8b493d52b4f 100644 --- a/include/asm-powerpc/sparsemem.h +++ b/include/asm-powerpc/sparsemem.h @@ -10,13 +10,8 @@ */ #define SECTION_SIZE_BITS 24 -#if defined(CONFIG_PS3_USE_LPAR_ADDR) -#define MAX_PHYSADDR_BITS 47 -#define MAX_PHYSMEM_BITS 47 -#else #define MAX_PHYSADDR_BITS 44 #define MAX_PHYSMEM_BITS 44 -#endif #ifdef CONFIG_MEMORY_HOTPLUG extern void create_section_mapping(unsigned long start, unsigned long end); diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index 34b7807f068b..f07c99ba5d13 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -104,6 +104,7 @@ struct spu_context; struct spu_runqueue; +struct spu_lscsa; struct device_node; enum spu_utilization_state { @@ -145,7 +146,6 @@ struct spu { void (* ibox_callback)(struct spu *spu); void (* stop_callback)(struct spu *spu); void (* mfc_callback)(struct spu *spu); - void (* dma_callback)(struct spu *spu, int type); char irq_c0[8]; char irq_c1[8]; @@ -196,10 +196,11 @@ struct cbe_spu_info { extern struct cbe_spu_info cbe_spu_info[]; void spu_init_channels(struct spu *spu); -int spu_irq_class_0_bottom(struct spu *spu); -int spu_irq_class_1_bottom(struct spu *spu); void spu_irq_setaffinity(struct spu *spu, int cpu); +void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, + void *code, int code_size); + #ifdef CONFIG_KEXEC void crash_register_spus(struct list_head *list); #else @@ -210,6 +211,7 @@ static inline void crash_register_spus(struct list_head *list) extern void spu_invalidate_slbs(struct spu *spu); extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); +int spu_64k_pages_available(void); /* Calls from the memory management to the SPU */ struct mm_struct; @@ -279,6 +281,8 @@ void spu_remove_sysdev_attr(struct sysdev_attribute *attr); int spu_add_sysdev_attr_group(struct attribute_group *attrs); void spu_remove_sysdev_attr_group(struct attribute_group *attrs); +int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, + unsigned long dsisr, unsigned *flt); /* * Notifier blocks: @@ -303,7 +307,7 @@ extern void notify_spus_active(void); extern void do_notify_spus_active(void); /* - * This defines the Local Store, Problem Area and Privlege Area of an SPU. + * This defines the Local Store, Problem Area and Privilege Area of an SPU. */ union mfc_tag_size_class_cmd { @@ -524,8 +528,24 @@ struct spu_priv1 { #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L +#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L u8 pad_0x118_0x140[0x28]; /* 0x118 */ u64 int_stat_RW[3]; /* 0x140 */ +#define CLASS0_DMA_ALIGNMENT_INTR 0x1L +#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L +#define CLASS0_SPU_ERROR_INTR 0x4L +#define CLASS0_INTR_MASK 0x7L +#define CLASS1_SEGMENT_FAULT_INTR 0x1L +#define CLASS1_STORAGE_FAULT_INTR 0x2L +#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L +#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L +#define CLASS1_INTR_MASK 0xfL +#define CLASS2_MAILBOX_INTR 0x1L +#define CLASS2_SPU_STOP_INTR 0x2L +#define CLASS2_SPU_HALT_INTR 0x4L +#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L +#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L +#define CLASS2_INTR_MASK 0x1fL u8 pad_0x158_0x180[0x28]; /* 0x158 */ u64 int_route_RW; /* 0x180 */ diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h index e87794d5d4ea..0ab6bff86078 100644 --- a/include/asm-powerpc/spu_csa.h +++ b/include/asm-powerpc/spu_csa.h @@ -194,7 +194,7 @@ struct spu_priv1_collapsed { }; /* - * struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads. + * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads. */ struct spu_priv2_collapsed { u64 slb_index_W; @@ -254,20 +254,11 @@ struct spu_state { u64 spu_chnldata_RW[32]; u32 spu_mailbox_data[4]; u32 pu_mailbox_data[1]; - u64 dar, dsisr; + u64 dar, dsisr, class_0_pending; unsigned long suspend_time; spinlock_t register_lock; }; -extern int spu_init_csa(struct spu_state *csa); -extern void spu_fini_csa(struct spu_state *csa); -extern int spu_save(struct spu_state *prev, struct spu *spu); -extern int spu_restore(struct spu_state *new, struct spu *spu); -extern int spu_switch(struct spu_state *prev, struct spu_state *new, - struct spu *spu); -extern int spu_alloc_lscsa(struct spu_state *csa); -extern void spu_free_lscsa(struct spu_state *csa); - #endif /* !__SPU__ */ #endif /* __KERNEL__ */ #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h index 0f37c7c90820..25020a34ce7f 100644 --- a/include/asm-powerpc/spu_priv1.h +++ b/include/asm-powerpc/spu_priv1.h @@ -24,6 +24,7 @@ #include <linux/types.h> struct spu; +struct spu_context; /* access to priv1 registers */ @@ -178,6 +179,8 @@ struct spu_management_ops { int (*enumerate_spus)(int (*fn)(void *data)); int (*create_spu)(struct spu *spu, void *data); int (*destroy_spu)(struct spu *spu); + void (*enable_spu)(struct spu_context *ctx); + void (*disable_spu)(struct spu_context *ctx); int (*init_affinity)(void); }; @@ -207,6 +210,18 @@ spu_init_affinity (void) return spu_management_ops->init_affinity(); } +static inline void +spu_enable_spu (struct spu_context *ctx) +{ + spu_management_ops->enable_spu(ctx); +} + +static inline void +spu_disable_spu (struct spu_context *ctx) +{ + spu_management_ops->disable_spu(ctx); +} + /* * The declarations folowing are put here for convenience * and only intended to be used by the platform setup code. diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h index 11d5383b2f09..0c8b0d679139 100644 --- a/include/asm-powerpc/systbl.h +++ b/include/asm-powerpc/systbl.h @@ -313,3 +313,4 @@ COMPAT_SYS_SPU(timerfd) SYSCALL_SPU(eventfd) COMPAT_SYS_SPU(sync_file_range2) COMPAT_SYS(fallocate) +SYSCALL(subpage_prot) diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h index 87be8c3bc9cb..bc9739dff5e7 100644 --- a/include/asm-powerpc/system.h +++ b/include/asm-powerpc/system.h @@ -169,6 +169,8 @@ extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); extern void bad_page_fault(struct pt_regs *, unsigned long, int); extern int die(const char *, struct pt_regs *, long); extern void _exception(int, struct pt_regs *, int, unsigned long); +extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + #ifdef CONFIG_BOOKE_WDT extern u32 booke_wdt_enabled; extern u32 booke_wdt_period; diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h index a9e0b0ebcb0f..6418ceea44b7 100644 --- a/include/asm-powerpc/udbg.h +++ b/include/asm-powerpc/udbg.h @@ -48,6 +48,7 @@ extern void __init udbg_init_rtas_console(void); extern void __init udbg_init_debug_beat(void); extern void __init udbg_init_btext(void); extern void __init udbg_init_44x_as1(void); +extern void __init udbg_init_40x_realmode(void); extern void __init udbg_init_cpm(void); #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h index 97d82b6a9406..fedc4b8e49e2 100644 --- a/include/asm-powerpc/unistd.h +++ b/include/asm-powerpc/unistd.h @@ -332,10 +332,11 @@ #define __NR_eventfd 307 #define __NR_sync_file_range2 308 #define __NR_fallocate 309 +#define __NR_subpage_prot 310 #ifdef __KERNEL__ -#define __NR_syscalls 310 +#define __NR_syscalls 311 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index 1311cefdfd30..4b0e15206006 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -123,7 +123,7 @@ typedef struct mem_ctlr { #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ #define OR_BI 0x00000100 /* Burst inhibit */ -#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ +#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/cpm1.h index 397248705e0e..03035acd85c6 100644 --- a/include/asm-ppc/commproc.h +++ b/include/asm-ppc/cpm1.h @@ -14,8 +14,8 @@ * IDMA1 space. The remaining DP RAM is available for buffer descriptors * or other use. */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ +#ifndef __CPM1__ +#define __CPM1__ #include <asm/8xx_immap.h> #include <asm/ptrace.h> @@ -72,13 +72,9 @@ extern int cpm_dpfree(unsigned long offset); extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8* addr); +extern uint cpm_dpram_phys(u8 *addr); extern void cpm_setbrg(uint brg, uint rate); -extern uint m8xx_cpm_hostalloc(uint size); -extern int m8xx_cpm_hostfree(uint start); -extern void m8xx_cpm_hostdump(void); - extern void cpm_load_patch(volatile immap_t *immr); /* Buffer descriptors used by many of the CPM protocols. @@ -681,7 +677,7 @@ typedef struct risc_timer_pram { #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ #define CICR_IEN ((uint)0x00000080) /* Int. enable */ #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ @@ -689,4 +685,4 @@ typedef struct risc_timer_pram { extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); extern void cpm_free_handler(int vec); -#endif /* __CPM_8XX__ */ +#endif /* __CPM1__ */ diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h index 12a2860f9a9c..4c538228e42f 100644 --- a/include/asm-ppc/cpm2.h +++ b/include/asm-ppc/cpm2.h @@ -90,7 +90,7 @@ */ #define CPM_DATAONLY_BASE ((uint)128) #define CPM_DP_NOSPACE ((uint)0x7fffffff) -#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) +#if defined(CONFIG_8272) #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) #else diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h deleted file mode 100644 index 9383d0c13ff8..000000000000 --- a/include/asm-ppc/immap_85xx.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * include/asm-ppc/immap_85xx.h - * - * MPC85xx Internal Memory Map - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IMMAP_85XX_H__ -#define __ASM_IMMAP_85XX_H__ - -/* Eventually this should define all the IO block registers in 85xx */ - -/* PCI Registers */ -typedef struct ccsr_pci { - uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ - uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ - uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ - uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ - char res2[4]; - uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ - char res3[12]; - uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ - uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ - char res4[4]; - uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ - char res5[12]; - uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ - uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ - char res6[4]; - uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ - char res7[12]; - uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ - uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ - char res8[4]; - uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ - char res9[12]; - uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ - uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ - char res10[4]; - uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ - char res11[268]; - uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ - char res12[4]; - uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ - char res13[12]; - uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ - char res14[4]; - uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ - char res15[12]; - uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ - char res16[4]; - uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ - char res17[4]; - uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ - char res18[12]; - uint err_dr; /* 0x.e00 - PCI Error Detect Register */ - uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ - uint err_en; /* 0x.e08 - PCI Error Enable Register */ - uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ - uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ - uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ - uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ - uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ - uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ - uint pci_timr; /* 0x.e24 - PCI Timer Register */ - char res19[472]; -} ccsr_pci_t; - -/* Global Utility Registers */ -typedef struct ccsr_guts { - uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ - uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - char res1[12]; - uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ - char res2[12]; - uint gpiocr; /* 0x.0030 - GPIO Control Register */ - char res3[12]; - uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ - char res4[12]; - uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ - char res5[12]; - uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - char res6[12]; - uint devdisr; /* 0x.0070 - Device Disable Control */ - char res7[12]; - uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - char res8[12]; - uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - char res9[12]; - uint pvr; /* 0x.00a0 - Processor Version Register */ - uint svr; /* 0x.00a4 - System Version Register */ - char res10[3416]; - uint clkocr; /* 0x.0e00 - Clock Out Select Register */ - char res11[12]; - uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ - char res12[12]; - uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - char res13[61916]; -} ccsr_guts_t; - -#endif /* __ASM_IMMAP_85XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 14584e505ed5..d46b57b589ae 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -383,6 +383,12 @@ typedef struct _P601_BAT { #define BOOKE_PAGESZ_256GB 14 #define BOOKE_PAGESZ_1TB 15 +#ifndef CONFIG_SERIAL_TEXT_DEBUG +#define PPC44x_EARLY_TLBS 1 +#else +#define PPC44x_EARLY_TLBS 2 +#endif + /* * Freescale Book-E MMU support */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h index b2e25d8997bf..9f097e25b169 100644 --- a/include/asm-ppc/mmu_context.h +++ b/include/asm-ppc/mmu_context.h @@ -64,11 +64,6 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) #define LAST_CONTEXT 255 #define FIRST_CONTEXT 1 -#elif defined(CONFIG_E200) || defined(CONFIG_E500) -#define NO_CONTEXT 256 -#define LAST_CONTEXT 255 -#define FIRST_CONTEXT 1 - #else /* PPC 6xx, 7xx CPUs */ diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h index c82b8d49a7da..39fcd02cd4e8 100644 --- a/include/asm-ppc/mpc52xx_psc.h +++ b/include/asm-ppc/mpc52xx_psc.h @@ -159,6 +159,9 @@ struct mpc52xx_psc { u8 reserved16[3]; u8 irfdr; /* PSC + 0x54 */ u8 reserved17[3]; +}; + +struct mpc52xx_psc_fifo { u16 rfnum; /* PSC + 0x58 */ u16 reserved18; u16 tfnum; /* PSC + 0x5c */ diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h deleted file mode 100644 index c3061972309b..000000000000 --- a/include/asm-ppc/mpc83xx.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * include/asm-ppc/mpc83xx.h - * - * MPC83xx definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MPC83xx_H__ -#define __ASM_MPC83xx_H__ - -#include <asm/mmu.h> - -#ifdef CONFIG_83xx - -#ifdef CONFIG_MPC834x_SYS -#include <platforms/83xx/mpc834x_sys.h> -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* Internal IRQs on MPC83xx OpenPIC */ -/* Not all of these exist on all MPC83xx implementations */ - -#ifndef MPC83xx_IPIC_IRQ_OFFSET -#define MPC83xx_IPIC_IRQ_OFFSET 0 -#endif - -#define NR_IPIC_INTS 128 - -#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET) - -#define MPC83xx_CCSRBAR_SIZE (1024*1024) - -/* Let modules/drivers get at immrbar (physical) */ -extern phys_addr_t immrbar; - -enum ppc_sys_devices { - MPC83xx_TSEC1, - MPC83xx_TSEC2, - MPC83xx_IIC1, - MPC83xx_IIC2, - MPC83xx_DUART, - MPC83xx_SEC2, - MPC83xx_USB2_DR, - MPC83xx_USB2_MPH, - MPC83xx_MDIO, - NUM_PPC_SYS_DEVS, -}; - -#endif /* CONFIG_83xx */ -#endif /* __ASM_MPC83xx_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h deleted file mode 100644 index d7e4a79d77fb..000000000000 --- a/include/asm-ppc/mpc85xx.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * include/asm-ppc/mpc85xx.h - * - * MPC85xx definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MPC85xx_H__ -#define __ASM_MPC85xx_H__ - -#include <asm/mmu.h> - -#ifdef CONFIG_85xx - -#ifdef CONFIG_MPC8540_ADS -#include <platforms/85xx/mpc8540_ads.h> -#endif -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) -#include <platforms/85xx/mpc8555_cds.h> -#endif -#ifdef CONFIG_MPC85xx_CDS -#include <platforms/85xx/mpc85xx_cds.h> -#endif -#ifdef CONFIG_MPC8560_ADS -#include <platforms/85xx/mpc8560_ads.h> -#endif -#ifdef CONFIG_SBC8560 -#include <platforms/85xx/sbc8560.h> -#endif -#ifdef CONFIG_STX_GP3 -#include <platforms/85xx/stx_gp3.h> -#endif -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \ - defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560) -#include <platforms/85xx/tqm85xx.h> -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* Offset from CCSRBAR */ -#define MPC85xx_CPM_OFFSET (0x80000) -#define MPC85xx_CPM_SIZE (0x40000) -#define MPC85xx_DMA_OFFSET (0x21000) -#define MPC85xx_DMA_SIZE (0x01000) -#define MPC85xx_DMA0_OFFSET (0x21100) -#define MPC85xx_DMA0_SIZE (0x00080) -#define MPC85xx_DMA1_OFFSET (0x21180) -#define MPC85xx_DMA1_SIZE (0x00080) -#define MPC85xx_DMA2_OFFSET (0x21200) -#define MPC85xx_DMA2_SIZE (0x00080) -#define MPC85xx_DMA3_OFFSET (0x21280) -#define MPC85xx_DMA3_SIZE (0x00080) -#define MPC85xx_ENET1_OFFSET (0x24000) -#define MPC85xx_ENET1_SIZE (0x01000) -#define MPC85xx_MIIM_OFFSET (0x24520) -#define MPC85xx_MIIM_SIZE (0x00018) -#define MPC85xx_ENET2_OFFSET (0x25000) -#define MPC85xx_ENET2_SIZE (0x01000) -#define MPC85xx_ENET3_OFFSET (0x26000) -#define MPC85xx_ENET3_SIZE (0x01000) -#define MPC85xx_GUTS_OFFSET (0xe0000) -#define MPC85xx_GUTS_SIZE (0x01000) -#define MPC85xx_IIC1_OFFSET (0x03000) -#define MPC85xx_IIC1_SIZE (0x00100) -#define MPC85xx_OPENPIC_OFFSET (0x40000) -#define MPC85xx_OPENPIC_SIZE (0x40000) -#define MPC85xx_PCI1_OFFSET (0x08000) -#define MPC85xx_PCI1_SIZE (0x01000) -#define MPC85xx_PCI2_OFFSET (0x09000) -#define MPC85xx_PCI2_SIZE (0x01000) -#define MPC85xx_PERFMON_OFFSET (0xe1000) -#define MPC85xx_PERFMON_SIZE (0x01000) -#define MPC85xx_SEC2_OFFSET (0x30000) -#define MPC85xx_SEC2_SIZE (0x10000) -#define MPC85xx_UART0_OFFSET (0x04500) -#define MPC85xx_UART0_SIZE (0x00100) -#define MPC85xx_UART1_OFFSET (0x04600) -#define MPC85xx_UART1_SIZE (0x00100) - -#define MPC85xx_CCSRBAR_SIZE (1024*1024) - -/* Let modules/drivers get at CCSRBAR */ -extern phys_addr_t get_ccsrbar(void); - -#ifdef MODULE -#define CCSRBAR get_ccsrbar() -#else -#define CCSRBAR BOARD_CCSRBAR -#endif - -enum ppc_sys_devices { - MPC85xx_TSEC1, - MPC85xx_TSEC2, - MPC85xx_FEC, - MPC85xx_IIC1, - MPC85xx_DMA0, - MPC85xx_DMA1, - MPC85xx_DMA2, - MPC85xx_DMA3, - MPC85xx_DUART, - MPC85xx_PERFMON, - MPC85xx_SEC2, - MPC85xx_CPM_SPI, - MPC85xx_CPM_I2C, - MPC85xx_CPM_USB, - MPC85xx_CPM_SCC1, - MPC85xx_CPM_SCC2, - MPC85xx_CPM_SCC3, - MPC85xx_CPM_SCC4, - MPC85xx_CPM_FCC1, - MPC85xx_CPM_FCC2, - MPC85xx_CPM_FCC3, - MPC85xx_CPM_MCC1, - MPC85xx_CPM_MCC2, - MPC85xx_CPM_SMC1, - MPC85xx_CPM_SMC2, - MPC85xx_eTSEC1, - MPC85xx_eTSEC2, - MPC85xx_eTSEC3, - MPC85xx_eTSEC4, - MPC85xx_IIC2, - MPC85xx_MDIO, - NUM_PPC_SYS_DEVS, -}; - -/* Internal interrupts are all Level Sensitive, and Positive Polarity */ -#define MPC85XX_INTERNAL_IRQ_SENSES \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */ - -#endif /* CONFIG_85xx */ -#endif /* __ASM_MPC85xx_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 063ad91cbbcc..69347bdbb401 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -271,48 +271,6 @@ extern unsigned long ioremap_bot, ioremap_base; /* ERPN in a PTE never gets cleared, ignore it */ #define _PTE_NONE_MASK 0xffffffff00000000ULL -#elif defined(CONFIG_FSL_BOOKE) -/* - MMU Assist Register 3: - - 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 - RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR - - - PRESENT *must* be in the bottom three bits because swap cache - entries use the top 29 bits. - - - FILE *must* be in the bottom three bits because swap cache - entries use the top 29 bits. -*/ - -/* Definitions for FSL Book-E Cores */ -#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ -#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ -#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */ -#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */ -#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */ -#define _PAGE_RW 0x00010 /* S: Write permission */ -#define _PAGE_HWEXEC 0x00020 /* H: UX permission */ - -#define _PAGE_ENDIAN 0x00040 /* H: E bit */ -#define _PAGE_GUARDED 0x00080 /* H: G bit */ -#define _PAGE_COHERENT 0x00100 /* H: M bit */ -#define _PAGE_NO_CACHE 0x00200 /* H: I bit */ -#define _PAGE_WRITETHRU 0x00400 /* H: W bit */ - -#ifdef CONFIG_PTE_64BIT -#define _PAGE_DIRTY 0x08000 /* S: Page dirty */ - -/* ERPN in a PTE never gets cleared, ignore it */ -#define _PTE_NONE_MASK 0xffffffffffff0000ULL -#else -#define _PAGE_DIRTY 0x00800 /* S: Page dirty */ -#endif - -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) - #elif defined(CONFIG_8xx) /* Definitions for 8xx embedded chips. */ #define _PAGE_PRESENT 0x0001 /* Page is valid */ @@ -484,11 +442,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); /* in some case we want to additionaly adjust where the pfn is in the pte to * allow room for more flags */ -#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) -#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8) -#else #define PFN_SHIFT_OFFSET (PAGE_SHIFT) -#endif #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) #define pte_page(x) pfn_to_page(pte_pfn(x)) diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h index de99e92d627b..d2fee41d600b 100644 --- a/include/asm-ppc/ppc_sys.h +++ b/include/asm-ppc/ppc_sys.h @@ -23,10 +23,6 @@ #if defined(CONFIG_8260) #include <asm/mpc8260.h> -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> -#elif defined(CONFIG_85xx) -#include <asm/mpc85xx.h> #elif defined(CONFIG_8xx) #include <asm/mpc8xx.h> #elif defined(CONFIG_PPC_MPC52xx) diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h index 6b7b63f71daa..3819e17cd7b0 100644 --- a/include/asm-ppc/ppcboot.h +++ b/include/asm-ppc/ppcboot.h @@ -38,8 +38,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\ - defined(CONFIG_83xx) +#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_PPC_MPC52xx) @@ -73,12 +72,11 @@ typedef struct bd_info { #if defined(CONFIG_HYMOD) hymod_conf_t bi_hymod_conf; /* hymod configuration information */ #endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ - defined(CONFIG_85xx) || defined(CONFIG_83xx) +#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) || defined(CONFIG_85xx) +#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) /* third onboard ethernet ports */ unsigned char bi_enet2addr[6]; #endif diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index 82948ed2744a..91e96af88bd8 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h @@ -207,7 +207,7 @@ #define CCR1_TCS 0x00000080 /* Timer Clock Select */ /* Bit definitions for the MCSR. */ -#ifdef CONFIG_440A +#ifdef CONFIG_4xx #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ @@ -218,32 +218,6 @@ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ #endif -#ifdef CONFIG_E500 -#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ -#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ -#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ -#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ -#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ -#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ -#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ -#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ -#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ -#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ -#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ -#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ -#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ -#endif -#ifdef CONFIG_E200 -#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ -#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ -#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ -#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn - fetch for an exception handler */ -#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ -#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ -#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered - store or cache line push */ -#endif /* Bit definitions for the DBSR. */ /* @@ -283,7 +257,7 @@ #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ #define ESR_PTR 0x02000000 /* Program Exception - Trap */ #define ESR_FP 0x01000000 /* Floating Point Operation */ #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index 8fc1b546613d..d35ed10315b1 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -29,10 +29,6 @@ #include <platforms/spruce.h> #elif defined(CONFIG_4xx) #include <asm/ibm4xx.h> -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> -#elif defined(CONFIG_85xx) -#include <asm/mpc85xx.h> #elif defined(CONFIG_RADSTONE_PPC7D) #include <platforms/radstone_ppc7d.h> #else diff --git a/include/linux/of.h b/include/linux/of.h index 5c39b9270ff7..b5f33efcb8e2 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -17,6 +17,7 @@ */ #include <linux/types.h> #include <linux/bitops.h> +#include <linux/mod_devicetable.h> #include <asm/prom.h> @@ -41,11 +42,20 @@ extern struct device_node *of_find_compatible_node(struct device_node *from, #define for_each_compatible_node(dn, type, compatible) \ for (dn = of_find_compatible_node(NULL, type, compatible); dn; \ dn = of_find_compatible_node(dn, type, compatible)) +extern struct device_node *of_find_matching_node(struct device_node *from, + const struct of_device_id *matches); +#define for_each_matching_node(dn, matches) \ + for (dn = of_find_matching_node(NULL, matches); dn; \ + dn = of_find_matching_node(dn, matches)) extern struct device_node *of_find_node_by_path(const char *path); extern struct device_node *of_find_node_by_phandle(phandle handle); extern struct device_node *of_get_parent(const struct device_node *node); extern struct device_node *of_get_next_child(const struct device_node *node, struct device_node *prev); +#define for_each_child_of_node(parent, child) \ + for (child = of_get_next_child(parent, NULL); child != NULL; \ + child = of_get_next_child(parent, child)) + extern struct property *of_find_property(const struct device_node *np, const char *name, int *lenp); @@ -56,5 +66,7 @@ extern const void *of_get_property(const struct device_node *node, int *lenp); extern int of_n_addr_cells(struct device_node *np); extern int of_n_size_cells(struct device_node *np); +extern const struct of_device_id *of_match_node( + const struct of_device_id *matches, const struct device_node *node); #endif /* _LINUX_OF_H */ diff --git a/include/linux/of_device.h b/include/linux/of_device.h index 212bffb2b174..6dc11959770c 100644 --- a/include/linux/of_device.h +++ b/include/linux/of_device.h @@ -10,8 +10,6 @@ #define to_of_device(d) container_of(d, struct of_device, dev) -extern const struct of_device_id *of_match_node( - const struct of_device_id *matches, const struct device_node *node); extern const struct of_device_id *of_match_device( const struct of_device_id *matches, const struct of_device *dev); diff --git a/include/linux/pata_platform.h b/include/linux/pata_platform.h index 5799e8d50623..6a7a92db294c 100644 --- a/include/linux/pata_platform.h +++ b/include/linux/pata_platform.h @@ -15,4 +15,13 @@ struct pata_platform_info { unsigned int irq_flags; }; +extern int __devinit __pata_platform_probe(struct device *dev, + struct resource *io_res, + struct resource *ctl_res, + struct resource *irq_res, + unsigned int ioport_shift, + int __pio_mask); + +extern int __devexit __pata_platform_remove(struct device *dev); + #endif /* __LINUX_PATA_PLATFORM_H */ diff --git a/include/linux/phy_fixed.h b/include/linux/phy_fixed.h index 04ba70d49fb8..509d8f5f984e 100644 --- a/include/linux/phy_fixed.h +++ b/include/linux/phy_fixed.h @@ -1,38 +1,31 @@ #ifndef __PHY_FIXED_H #define __PHY_FIXED_H -#define MII_REGS_NUM 29 - -/* max number of virtual phy stuff */ -#define MAX_PHY_AMNT 10 -/* - The idea is to emulate normal phy behavior by responding with - pre-defined values to mii BMCR read, so that read_status hook could - take all the needed info. -*/ - struct fixed_phy_status { - u8 link; - u16 speed; - u8 duplex; + int link; + int speed; + int duplex; + int pause; + int asym_pause; }; -/*----------------------------------------------------------------------------- - * Private information hoder for mii_bus - *-----------------------------------------------------------------------------*/ -struct fixed_info { - u16 *regs; - u8 regs_num; - struct fixed_phy_status phy_status; - struct phy_device *phydev; /* pointer to the container */ - /* link & speed cb */ - int (*link_update) (struct net_device *, struct fixed_phy_status *); +#ifdef CONFIG_FIXED_PHY +extern int fixed_phy_add(unsigned int irq, int phy_id, + struct fixed_phy_status *status); +#else +static inline int fixed_phy_add(unsigned int irq, int phy_id, + struct fixed_phy_status *status) +{ + return -ENODEV; +} +#endif /* CONFIG_FIXED_PHY */ -}; - - -int fixed_mdio_set_link_update(struct phy_device *, - int (*link_update) (struct net_device *, struct fixed_phy_status *)); -struct fixed_info *fixed_mdio_get_phydev (int phydev_ind); +/* + * This function issued only by fixed_phy-aware drivers, no need + * protect it with #ifdef + */ +extern int fixed_phy_set_link_update(struct phy_device *phydev, + int (*link_update)(struct net_device *, + struct fixed_phy_status *)); #endif /* __PHY_FIXED_H */ diff --git a/include/linux/pmu.h b/include/linux/pmu.h index b7824c215354..4c5f65392d36 100644 --- a/include/linux/pmu.h +++ b/include/linux/pmu.h @@ -159,41 +159,7 @@ extern void pmu_unlock(void); extern int pmu_present(void); extern int pmu_get_model(void); -#ifdef CONFIG_PM -/* - * Stuff for putting the powerbook to sleep and waking it again. - * - */ -#include <linux/list.h> - -struct pmu_sleep_notifier -{ - void (*notifier_call)(struct pmu_sleep_notifier *self, int when); - int priority; - struct list_head list; -}; - -/* Code values for calling sleep/wakeup handlers - */ -#define PBOOK_SLEEP_REQUEST 1 -#define PBOOK_SLEEP_NOW 2 -#define PBOOK_WAKE 3 - -/* priority levels in notifiers */ -#define SLEEP_LEVEL_VIDEO 100 /* Video driver (first wake) */ -#define SLEEP_LEVEL_MEDIABAY 90 /* Media bay driver */ -#define SLEEP_LEVEL_BLOCK 80 /* IDE, SCSI */ -#define SLEEP_LEVEL_NET 70 /* bmac, gmac */ -#define SLEEP_LEVEL_MISC 60 /* Anything else */ -#define SLEEP_LEVEL_USERLAND 55 /* Reserved for apm_emu */ -#define SLEEP_LEVEL_ADB 50 /* ADB (async) */ -#define SLEEP_LEVEL_SOUND 40 /* Sound driver (blocking) */ - -/* special register notifier functions */ -int pmu_register_sleep_notifier(struct pmu_sleep_notifier* notifier); -int pmu_unregister_sleep_notifier(struct pmu_sleep_notifier* notifier); - -#endif /* CONFIG_PM */ +extern void pmu_backlight_set_sleep(int sleep); #define PMU_MAX_BATTERIES 2 |