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| author | Ofir Bitton <obitton@habana.ai> | 2020-07-21 10:49:51 +0300 |
|---|---|---|
| committer | Oded Gabbay <oded.gabbay@gmail.com> | 2020-09-22 18:49:49 +0300 |
| commit | 0a068adde505a90ece23caaf19b77567e1d18298 (patch) | |
| tree | bb4a8b951eef94143747d05ac8ef68c19d1549ba /include/uapi/misc | |
| parent | a98d73c7fae486f7fea83bdec8599d4fccb6807d (diff) | |
| download | lwn-0a068adde505a90ece23caaf19b77567e1d18298.tar.gz lwn-0a068adde505a90ece23caaf19b77567e1d18298.zip | |
habanalabs: add information about PCIe controller
Update firmware header with new API for getting pcie info
such as tx/rx throughput and replay counter.
These counters are needed by customers for monitor and maintenance
of multiple devices.
Add new opcodes to the INFO ioctl to retrieve these counters.
Signed-off-by: Ofir Bitton <obitton@habana.ai>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat (limited to 'include/uapi/misc')
| -rw-r--r-- | include/uapi/misc/habanalabs.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index d5c4f983b7a8..ee13b919db35 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -264,6 +264,8 @@ enum hl_device_status { * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time * for synchronization. * HL_INFO_CS_COUNTERS - Retrieve command submission counters + * HL_INFO_PCI_COUNTERS - Retrieve PCI counters + * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -276,6 +278,8 @@ enum hl_device_status { #define HL_INFO_RESET_COUNT 9 #define HL_INFO_TIME_SYNC 10 #define HL_INFO_CS_COUNTERS 11 +#define HL_INFO_PCI_COUNTERS 12 +#define HL_INFO_CLK_THROTTLE_REASON 13 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -341,6 +345,29 @@ struct hl_info_time_sync { }; /** + * struct hl_info_pci_counters - pci counters + * @rx_throughput: PCI rx throughput KBps + * @tx_throughput: PCI tx throughput KBps + * @replay_cnt: PCI replay counter + */ +struct hl_info_pci_counters { + __u64 rx_throughput; + __u64 tx_throughput; + __u64 replay_cnt; +}; + +#define HL_CLK_THROTTLE_POWER 0x1 +#define HL_CLK_THROTTLE_THERMAL 0x2 + +/** + * struct hl_info_clk_throttle - clock throttling reason + * @clk_throttling_reason: each bit represents a clk throttling reason + */ +struct hl_info_clk_throttle { + __u32 clk_throttling_reason; +}; + +/** * struct hl_info_cs_counters - command submission counters * @out_of_mem_drop_cnt: dropped due to memory allocation issue * @parsing_drop_cnt: dropped due to error in packet parsing |