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| author | David E. Box <david.e.box@linux.intel.com> | 2020-10-28 18:44:45 -0700 |
|---|---|---|
| committer | Lee Jones <lee.jones@linaro.org> | 2020-11-04 11:13:35 +0000 |
| commit | 1dc2da5cd51f648de6d1df87e2bc6ea13f72f19c (patch) | |
| tree | 9d019682961341afb96d8dc56b7d49d03adf1bac /include/uapi/linux/pci_regs.h | |
| parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
| download | lwn-1dc2da5cd51f648de6d1df87e2bc6ea13f72f19c.tar.gz lwn-1dc2da5cd51f648de6d1df87e2bc6ea13f72f19c.zip | |
PCI: Add defines for Designated Vendor-Specific Extended Capability
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index a95d55f9f257..8f8bd2318c6c 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -723,6 +723,7 @@ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT @@ -1066,6 +1067,10 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ +#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ +#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ + /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ |