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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-01-13 16:48:54 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2022-02-25 12:36:25 +0100 |
| commit | 9584e7263e9ebcd94b184dc3efc847355a624220 (patch) | |
| tree | 9c1c07f2a65d6329d072f7fcfe0965b865f282d6 /include/soc | |
| parent | 9a0775c9cd3d89d1fe957a137131681a33f5736b (diff) | |
| download | lwn-9584e7263e9ebcd94b184dc3efc847355a624220.tar.gz lwn-9584e7263e9ebcd94b184dc3efc847355a624220.zip | |
ARM: at91: PM: add cpu idle support for sama7g5
Add CPU idle support for SAMA7G5. Support will make use of PMC_CPU_RATIO
register to divide the CPU clock by 16 before switching it to idle and
use automatic self-refresh option of DDR controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220113144900.906370-5-claudiu.beznea@microchip.com
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/at91/sama7-ddr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index fee1b11bddca..9e17247474fa 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -53,6 +53,7 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ +#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */ #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ |