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| author | Stephen Warren <swarren@nvidia.com> | 2011-05-17 16:12:36 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-19 16:51:01 -0700 |
| commit | 4539c24fe4f92c09ee668ef959d3e8180df619b9 (patch) | |
| tree | d198ea0f07a6f6ba697747d6243ce6b89c319091 /include/linux/serial_core.h | |
| parent | ee4f6b4b89665b92ead67deaa2e5d2ffa1af2b5f (diff) | |
| download | lwn-4539c24fe4f92c09ee668ef959d3e8180df619b9.tar.gz lwn-4539c24fe4f92c09ee668ef959d3e8180df619b9.zip | |
tty/serial: Add explicit PORT_TEGRA type
Tegra's UART is currently auto-detected as PORT_XSCALE due to register
bit UART_IER.UUE being writable. However, the Tegra documentation states
that this register bit is reserved. Hence, we should not program it.
Instead, the documentation specifies that the UART is 16550 compatible.
However, Tegra does need register bit UART_IER.RTOIE set, which is not
enabled by any 16550 port type. This was not noticed before, since
PORT_XSCALE enables CAP_UUE, which conflates both UUE and RTOIE bit
programming.
This change defines PORT_TEGRA that doesn't set UART_CAP_UUE, but does
set UART_CAP_RTOIE, which is a new capability indicating that the RTOIE
bit needs to be enabled.
Based-on-code-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/serial_core.h')
| -rw-r--r-- | include/linux/serial_core.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 95d479ba514e..a5c31146a337 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -45,7 +45,8 @@ #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ -#define PORT_MAX_8250 19 /* max port ID */ +#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ +#define PORT_MAX_8250 20 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed |