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authorGuo Zeng <Guo.Zeng@csr.com>2015-09-17 05:23:20 +0000
committerMark Brown <broonie@kernel.org>2015-09-17 11:46:09 +0100
commit7b7d1968e4c8d8392e8e63906d45d0bcad079037 (patch)
tree7fe40619a35b3a075523b799b4b47f46c667a4e2 /include/linux/regmap.h
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f (diff)
downloadlwn-7b7d1968e4c8d8392e8e63906d45d0bcad079037.tar.gz
lwn-7b7d1968e4c8d8392e8e63906d45d0bcad079037.zip
regmap: irq: add support for chips who have separate unmask registers
Some chips have separate unmask registers from mask registers for some consideration of concurrency SMP write performance. And this patch adds a flag for it. An user will be CSR SiRFSoC ARM chips. Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/regmap.h')
-rw-r--r--include/linux/regmap.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 8fc0bfd8edc4..f98fe9f5faa2 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -800,6 +800,8 @@ struct regmap_irq {
*
* @status_base: Base status register address.
* @mask_base: Base mask register address.
+ * @unmask_base: Base unmask register address. for chips who have
+ * separate mask and unmask registers
* @ack_base: Base ack address. If zero then the chip is clear on read.
* Using zero value is possible with @use_ack bit.
* @wake_base: Base address for wake enables. If zero unsupported.
@@ -820,6 +822,7 @@ struct regmap_irq_chip {
unsigned int status_base;
unsigned int mask_base;
+ unsigned int unmask_base;
unsigned int ack_base;
unsigned int wake_base;
unsigned int irq_reg_stride;