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| author | Keith Busch <keith.busch@intel.com> | 2016-09-27 16:23:34 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-09-27 16:01:49 -0500 |
| commit | 66b808099146166c44157600a166c8372172cd76 (patch) | |
| tree | 6dfd3e4ab300a3a3d07a6d546f8a1404c5d0f105 /include/linux/pci.h | |
| parent | 4b202b716e4e282c26c4a95952ea33e318c363ab (diff) | |
| download | lwn-66b808099146166c44157600a166c8372172cd76.tar.gz lwn-66b808099146166c44157600a166c8372172cd76.zip | |
PCI/AER: Cache capability position
Save the position of the error reporting capability so it doesn't need to
be rediscovered during error handling.
Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Lukas Wunner <lukas@wunner.de>
Diffstat (limited to 'include/linux/pci.h')
| -rw-r--r-- | include/linux/pci.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 57bc838e0666..ab6b02763916 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -269,6 +269,9 @@ struct pci_dev { unsigned int class; /* 3 bytes: (base,sub,prog-if) */ u8 revision; /* PCI revision, low byte of class word */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */ +#ifdef CONFIG_PCIEAER + u16 aer_cap; /* AER capability offset */ +#endif u8 pcie_cap; /* PCIe capability offset */ u8 msi_cap; /* MSI capability offset */ u8 msix_cap; /* MSI-X capability offset */ @@ -1369,9 +1372,11 @@ static inline bool pcie_aspm_support_enabled(void) { return false; } #ifdef CONFIG_PCIEAER void pci_no_aer(void); bool pci_aer_available(void); +int pci_aer_init(struct pci_dev *dev); #else static inline void pci_no_aer(void) { } static inline bool pci_aer_available(void) { return false; } +static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } #endif #ifdef CONFIG_PCIE_ECRC |