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| author | Simon Horman <horms@verge.net.au> | 2010-11-27 00:11:55 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-29 12:54:55 +0900 |
| commit | 22efa0fee32d9e7f6f6fbc396a872b5708d86048 (patch) | |
| tree | e5ed9af4fcb68b6c44f25e88a3e97fcb68c681c9 /include/linux/mmc/sh_mmcif.h | |
| parent | 1ae0affedce1d3e401991fbe7f2674753f0a7641 (diff) | |
| download | lwn-22efa0fee32d9e7f6f6fbc396a872b5708d86048.tar.gz lwn-22efa0fee32d9e7f6f6fbc396a872b5708d86048.zip | |
sh, mmc: Use defines when setting CE_CLK_CTRL
The 16-19th bits of CE_CLK_CTRL set the
MMC clock frequency.
Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/linux/mmc/sh_mmcif.h')
| -rw-r--r-- | include/linux/mmc/sh_mmcif.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h index 342ec1a38684..ffabf8c0a531 100644 --- a/include/linux/mmc/sh_mmcif.h +++ b/include/linux/mmc/sh_mmcif.h @@ -70,6 +70,9 @@ struct sh_mmcif_plat_data { #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) +#define CLKDIV_4 (1<<16) /* mmc clock frequency. + * n: bus clock/(2^(n+1)) */ +#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */ #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ (1 << 9) | (1 << 8)) /* resp busy timeout */ @@ -178,14 +181,10 @@ static inline void sh_mmcif_boot_init(void __iomem *base) /* Set block size in MMCIF hardware */ sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); - /* Enable the clock, set it to Bus clock/256 (about 325Khz). - * It is unclear where 0x70000 comes from or if it is even needed. - * It is there for byte-compatibility with code that is known to - * work. - */ + /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, - CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | - SCCSTO_29 | 0x70000); + CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD0 */ sh_mmcif_boot_cmd(base, 0x00000040, 0); @@ -210,7 +209,9 @@ static inline void sh_mmcif_boot_slurp(void __iomem *base, unsigned long tmp; /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ - sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff); + sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, + CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | + SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); /* CMD9 - Get CSD */ sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); |