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authorSylwester Nawrocki <s.nawrocki@samsung.com>2016-04-15 18:57:00 +0200
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-04-15 18:57:00 +0200
commit6466ee322749e7f440764df053ccccb2d15ab4de (patch)
tree479b4c0cf10d6af2576275947bde31e93773bb72 /include/dt-bindings
parentf6764714afdde1f0f511bb0e2d531593c3bec827 (diff)
parent81fed6e342c04a4ecb0650c914d24bd57c6c168f (diff)
downloadlwn-6466ee322749e7f440764df053ccccb2d15ab4de.tar.gz
lwn-6466ee322749e7f440764df053ccccb2d15ab4de.zip
Merge branch 'for-v4.7/clk/exynos542x' into for-v4.7/clk/next
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5420.h24
1 files changed, 23 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 7699ee9c16c0..17ab8394bec7 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -217,8 +217,30 @@
/* divider clocks */
#define CLK_DOUT_PIXEL 768
+#define CLK_DOUT_ACLK400_WCORE 769
+#define CLK_DOUT_ACLK400_ISP 770
+#define CLK_DOUT_ACLK400_MSCL 771
+#define CLK_DOUT_ACLK200 772
+#define CLK_DOUT_ACLK200_FSYS2 773
+#define CLK_DOUT_ACLK100_NOC 774
+#define CLK_DOUT_PCLK200_FSYS 775
+#define CLK_DOUT_ACLK200_FSYS 776
+#define CLK_DOUT_ACLK333_432_GSCL 777
+#define CLK_DOUT_ACLK333_432_ISP 778
+#define CLK_DOUT_ACLK66 779
+#define CLK_DOUT_ACLK333_432_ISP0 780
+#define CLK_DOUT_ACLK266 781
+#define CLK_DOUT_ACLK166 782
+#define CLK_DOUT_ACLK333 783
+#define CLK_DOUT_ACLK333_G2D 784
+#define CLK_DOUT_ACLK266_G2D 785
+#define CLK_DOUT_ACLK_G3D 786
+#define CLK_DOUT_ACLK300_JPEG 787
+#define CLK_DOUT_ACLK300_DISP1 788
+#define CLK_DOUT_ACLK300_GSCL 789
+#define CLK_DOUT_ACLK400_DISP1 790
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 769
+#define CLK_NR_CLKS 791
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */