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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-08-19 14:49:26 +0900 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-08-20 18:28:39 -0700 |
| commit | f2032f24c0e51487d88c3555db12e27d561e4f14 (patch) | |
| tree | d7b2cf20932073c6c7589a4d2b94dddffaaf2166 /include/dt-bindings/reset | |
| parent | 62060a3548c5ea038b4ade518cce92be32a6718d (diff) | |
| download | lwn-f2032f24c0e51487d88c3555db12e27d561e4f14.tar.gz lwn-f2032f24c0e51487d88c3555db12e27d561e4f14.zip | |
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask. Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/dt-bindings/reset')
0 files changed, 0 insertions, 0 deletions