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| author | Rob Herring (Arm) <robh@kernel.org> | 2025-12-12 17:11:52 -0600 |
|---|---|---|
| committer | Rob Herring (Arm) <robh@kernel.org> | 2026-02-03 20:58:09 -0600 |
| commit | ff7e082ea40d70b7613e8db2cb11e3555ebcc546 (patch) | |
| tree | f75f19924968a8178b74b89fb319ff9f934418af /include/dt-bindings/memory | |
| parent | 180547ebd86cdb089f657c0666de8853a2d1571c (diff) | |
| download | lwn-ff7e082ea40d70b7613e8db2cb11e3555ebcc546.tar.gz lwn-ff7e082ea40d70b7613e8db2cb11e3555ebcc546.zip | |
dt-bindings: Remove unused includes
Remove includes which are not referenced by either DTS files or drivers.
There's a few more which are new, so they are excluded for now.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251212231203.727227-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to 'include/dt-bindings/memory')
| -rw-r--r-- | include/dt-bindings/memory/mt6779-larb-port.h | 206 |
1 files changed, 0 insertions, 206 deletions
diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h deleted file mode 100644 index 3fb438a96e35..000000000000 --- a/include/dt-bindings/memory/mt6779-larb-port.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Chao Hao <chao.hao@mediatek.com> - */ - -#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 -#define M4U_LARB8_ID 8 -#define M4U_LARB9_ID 9 -#define M4U_LARB10_ID 10 -#define M4U_LARB11_ID 11 - -/* larb0 */ -#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) - -/* larb1 */ -#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) -#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) -#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) -#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) - -/* larb2-VDEC */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) - -/* larb3-VENC */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) -#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) - -/* larb4-dummy */ - -/* larb5-IMG */ -#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) -#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) -#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) -#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) -#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) -#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) -#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) -#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) -#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) -#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) -#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) -#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) -#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) -#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) -#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) -#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) -#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) -#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) - -/* larb6-IMG-VPU */ -#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) - -/* larb7-DVS */ -#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) -#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) -#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) - -/* larb8-IPESYS */ -#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) -#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) -#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) -#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) -#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) -#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) -#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) -#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) -#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) -#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) - -/* larb9-CAM */ -#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) -#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) -#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) -#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) -#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) -#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) -#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) -#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) -#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) -#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) -#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) -#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) -#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) -#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) -#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) -#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) -#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) -#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) -#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) -#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) -#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) -#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) -#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) -#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) - -/* larb10-CAM_A */ -#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) -#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) -#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) -#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) -#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) -#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) -#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) -#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) -#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) -#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) -#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) -#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) -#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) -#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) -#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) -#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) -#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) -#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) -#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) -#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) -#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) -#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) -#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) -#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) -#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) -#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) -#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) -#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) -#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) -#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) -#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) - -/* larb11-CAM-VPU */ -#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) -#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) -#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) -#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) -#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) - -#endif |