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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-06-14 16:37:20 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-06-18 10:49:57 -0700 |
| commit | e364672477a105029346f0888bfa797b1ec3eee4 (patch) | |
| tree | 870aa04f8030b1bc6dadc39efae2c7380265f762 /include/drm/i915_pciids.h | |
| parent | b9be78531d2710f4302545aa80e0678ed0a3dd09 (diff) | |
| download | lwn-e364672477a105029346f0888bfa797b1ec3eee4.tar.gz lwn-e364672477a105029346f0888bfa797b1ec3eee4.zip | |
drm/i915/aml: Introducing Amber Lake platform
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that
now is moved to AML page.
So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it will be handled as a KBL.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180614233720.30517-2-jose.souza@intel.com
Diffstat (limited to 'include/drm/i915_pciids.h')
| -rw-r--r-- | include/drm/i915_pciids.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index d03350a38025..fbf5cfc9b352 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -349,7 +349,6 @@ #define INTEL_KBL_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ - INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ @@ -365,11 +364,17 @@ #define INTEL_KBL_GT4_IDS(info) \ INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ +/* AML/KBL Y GT2 */ +#define INTEL_AML_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */ + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ INTEL_KBL_GT3_IDS(info), \ - INTEL_KBL_GT4_IDS(info) + INTEL_KBL_GT4_IDS(info), \ + INTEL_AML_GT2_IDS(info) /* CFL S */ #define INTEL_CFL_S_GT1_IDS(info) \ |