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| author | Chris Zankel <czankel@tensilica.com> | 2006-12-10 02:18:47 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-10 09:55:39 -0800 |
| commit | fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0 (patch) | |
| tree | 5225910274cbf362143a80b95b6b38c4a7d22e6d /include/asm-xtensa/byteorder.h | |
| parent | 5fcf7bb73f66cc1c4ad90788b0f367c4d6852b75 (diff) | |
| download | lwn-fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0.tar.gz lwn-fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0.zip | |
[PATCH] xtensa: fix irq and misc fixes
Update the architecture specific interrupt handling code for Xtensa to support
the new API. Use generic BUG macros in bug.h, and some minor fixes.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-xtensa/byteorder.h')
| -rw-r--r-- | include/asm-xtensa/byteorder.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h index 0b1552569aae..0ba72ddbf889 100644 --- a/include/asm-xtensa/byteorder.h +++ b/include/asm-xtensa/byteorder.h @@ -14,7 +14,7 @@ #include <asm/processor.h> #include <asm/types.h> -static __inline__ __const__ __u32 ___arch__swab32(__u32 x) +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) { __u32 res; /* instruction sequence from Xtensa ISA release 2/2000 */ @@ -29,7 +29,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x) return res; } -static __inline__ __const__ __u16 ___arch__swab16(__u16 x) +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) { /* Given that 'short' values are signed (i.e., can be negative), * we cannot assume that the upper 16-bits of the register are |