diff options
| author | Vitaly Bordug <vbordug@ru.mvista.com> | 2005-09-16 19:28:00 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-17 11:50:01 -0700 |
| commit | 514ccd4e6c414d8064d53235f7fc09fc02ec2078 (patch) | |
| tree | 37f0b4f70fab7cf3ef1bf80cee430950744ecb1b /include/asm-ppc/irq.h | |
| parent | 0faf3d3d08bb20d803ba090a1bc1ffedaea6ced6 (diff) | |
| download | lwn-514ccd4e6c414d8064d53235f7fc09fc02ec2078.tar.gz lwn-514ccd4e6c414d8064d53235f7fc09fc02ec2078.zip | |
[PATCH] ppc32: Add ppc_sys descriptions for PowerQUICC I devices
Added ppc_sys device and system definitions for PowerQUICC I devices. This
will allow drivers for PQI to be proper platform device drivers. Currently
sys section contains only MPC885 and MPC866. Identification should be done
with identify_ppc_sys_by_name call, with board-specific "name" string
passed, since PQI do not have any register that could identify the SOC.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc/irq.h')
| -rw-r--r-- | include/asm-ppc/irq.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index 55752474d0d9..bd9674807f05 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -138,6 +138,16 @@ irq_canonicalize(int irq) #define SIU_IRQ7 (14) #define SIU_LEVEL7 (15) +#define MPC8xx_INT_FEC1 SIU_LEVEL1 +#define MPC8xx_INT_FEC2 SIU_LEVEL3 + +#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1) +#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2) +#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3) +#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4) +#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1) +#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2) + /* The internal interrupts we can configure as we see fit. * My personal preference is CPM at level 2, which puts it above the * MBX PCI/ISA/IDE interrupts. |