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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 19:07:12 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 19:07:12 -0700
commit25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (patch)
treee0977d906193eadeafebc442775491b844be79d5 /include/asm-mips/mach-wrppmc/mach-gt64120.h
parent4c84a39c8adba6bf2f829b217e78bfd61478191a (diff)
parent1723b4a34af85447684c9696af83929d2c1e8e6b (diff)
downloadlwn-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.tar.gz
lwn-25f42b6af09e34c3f92107b36b5aa6edc2fdba2f.zip
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits) [MIPS] Make timer interrupt frequency configurable from kconfig. [MIPS] Correct HAL2 Kconfig description [MIPS] Fix R4K cache macro names [MIPS] Add Missing R4K Cache Macros to IP27 & IP32 [MIPS] Support for the RM9000-based Basler eXcite smart camera platform. [MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board [MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors. [MIPS] SN: include asm/sn/types.h for nasid_t. [MIPS] Random fixes for sb1250 [MIPS] Fix bcm1480 compile [MIPS] Remove support for NEC DDB5476. [MIPS] Remove support for NEC DDB5074. [MIPS] Cleanup memory managment initialization. [MIPS] SN: Declare bridge_pci_ops. [MIPS] Remove unused function alloc_pci_controller. [MIPS] IP27: Extract pci_ops into separate file. [MIPS] IP27: Use symbolic constants instead of magic numbers. [MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig. [MIPS] IP27: Cleanup N/M mode configuration. [MIPS] IP27: Throw away old unused hacks. ...
Diffstat (limited to 'include/asm-mips/mach-wrppmc/mach-gt64120.h')
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h84
1 files changed, 84 insertions, 0 deletions
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
new file mode 100644
index 000000000000..ba9205a04582
--- /dev/null
+++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h
@@ -0,0 +1,84 @@
+/*
+ * This is a direct copy of the ev96100.h file, with a global
+ * search and replace. The numbers are the same.
+ *
+ * The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef __ASM_MIPS_GT64120_H
+#define __ASM_MIPS_GT64120_H
+
+/*
+ * This is the CPU physical memory map of PPMC Board:
+ *
+ * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
+ * 0x1C000000-0x1C000000 - LED (CS0)
+ * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
+ * 0x1F000000-0x1F000000 - MailBox (CS3)
+ * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
+ */
+
+#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
+#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
+
+#define WRPPMC_UART16550_BASE 0x1C800000
+#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
+
+#define WRPPMC_LED_BASE 0x1C000000
+#define WRPPMC_MBOX_BASE 0x1F000000
+
+#define WRPPMC_BOOTROM_BASE 0x1FC00000
+#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
+
+#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
+#define WRPPMC_UART16550_IRQ 6
+#define WRPPMC_PCI_INTA_IRQ 3
+
+/*
+ * PCI Bus I/O and Memory resources allocation
+ *
+ * NOTE: We only have PCI_0 hose interface
+ */
+#define GT_PCI_MEM_BASE 0x13000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE 0x11000000UL
+#define GT_PCI_IO_SIZE 0x02000000UL
+#define GT_ISA_IO_BASE PCI_IO_BASE
+
+/*
+ * PCI interrupts will come in on either the INTA or INTD interrups lines,
+ * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
+ * boards, they all either come in on IntD or they all come in on IntA, they
+ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
+ * "requested" interrupt numbers and go through the list whenever we get an
+ * IntA/D.
+ *
+ * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
+ * INTD is 11.
+ */
+#define GT_TIMER 4
+#define GT_INTA 2
+#define GT_INTD 5
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GT64120 internal register space base address
+ */
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE (gt64120_base)
+
+/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
+#undef WRPPMC_EARLY_DEBUG
+
+#ifdef WRPPMC_EARLY_DEBUG
+extern void wrppmc_led_on(int mask);
+extern void wrppmc_led_off(int mask);
+extern void wrppmc_early_printk(const char *fmt, ...);
+#else
+#define wrppmc_early_printk(fmt, ...) do {} while (0)
+#endif /* WRPPMC_EARLY_DEBUG */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_MIPS_GT64120_H */