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| author | José Roberto de Souza <jose.souza@intel.com> | 2020-01-22 10:26:16 -0800 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-01-24 10:30:07 -0800 |
| commit | 58c34c4ca392ac9e658ee31f32db58abdf9fa352 (patch) | |
| tree | e2d4e76051ca5b8bdb656c99296ac6100a9fbdfd /drivers | |
| parent | de409661c4c90d63cfc64579edbad0a6b10bd50d (diff) | |
| download | lwn-58c34c4ca392ac9e658ee31f32db58abdf9fa352.tar.gz lwn-58c34c4ca392ac9e658ee31f32db58abdf9fa352.zip | |
drm/i915/dc3co: Do the full calculation of DC3CO exit only once
This will calculaet the DC3CO exit delay only once per full modeset.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200122182617.18597-1-jose.souza@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7f4056057f0c..538662ce1b3d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -802,8 +802,10 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; - dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state); dev_priv->psr.transcoder = crtc_state->cpu_transcoder; + /* DC5/DC6 requires at least 6 idle frames */ + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); + dev_priv->psr.dc3co_exit_delay = val; /* * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR @@ -1277,8 +1279,6 @@ static void tgl_dc3co_flush(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits, enum fb_op_origin origin) { - u32 delay; - mutex_lock(&dev_priv->psr.lock); if (!dev_priv->psr.dc3co_enabled) @@ -1296,10 +1296,8 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv, goto unlock; tgl_psr2_enable_dc3co(dev_priv); - /* DC5/DC6 required idle frames = 6 */ - delay = 6 * dev_priv->psr.dc3co_exit_delay; mod_delayed_work(system_wq, &dev_priv->psr.idle_work, - usecs_to_jiffies(delay)); + dev_priv->psr.dc3co_exit_delay); unlock: mutex_unlock(&dev_priv->psr.lock); |