diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-02-17 15:16:56 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-02-17 17:27:35 -0800 |
| commit | a4153d401ac440c73e0721db0b6b031e8e6f77d1 (patch) | |
| tree | 9ae5458a45ee018108515929f905bab457d351cf /drivers | |
| parent | d110114281fad580dd9ce629507d17b123169cff (diff) | |
| download | lwn-a4153d401ac440c73e0721db0b6b031e8e6f77d1.tar.gz lwn-a4153d401ac440c73e0721db0b6b031e8e6f77d1.zip | |
tg3: Add support for 2 new selfboot formats
This patch adds new offsets to the bootcode version extraction code to
support NVRAM format versions 4 and 5.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tg3.c | 6 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 051b18ad3f0c..f08e4b846458 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -12753,6 +12753,12 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) case TG3_EEPROM_SB_REVISION_3: offset = TG3_EEPROM_SB_F1R3_EDH_OFF; break; + case TG3_EEPROM_SB_REVISION_4: + offset = TG3_EEPROM_SB_F1R4_EDH_OFF; + break; + case TG3_EEPROM_SB_REVISION_5: + offset = TG3_EEPROM_SB_F1R5_EDH_OFF; + break; default: return; } diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index b4fd59623cfb..ffc12b1cb388 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1864,6 +1864,8 @@ #define TG3_EEPROM_SB_REVISION_0 0x00000000 #define TG3_EEPROM_SB_REVISION_2 0x00020000 #define TG3_EEPROM_SB_REVISION_3 0x00030000 +#define TG3_EEPROM_SB_REVISION_4 0x00040000 +#define TG3_EEPROM_SB_REVISION_5 0x00050000 #define TG3_EEPROM_MAGIC_HW 0xabcd #define TG3_EEPROM_MAGIC_HW_MSK 0xffff @@ -1881,6 +1883,8 @@ #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 +#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c +#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff |