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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-02-11 19:52:06 +0200 |
---|---|---|
committer | Ben Hutchings <ben@decadent.org.uk> | 2014-04-02 00:58:51 +0100 |
commit | 13f09b941bc8cfb1a1355a26c999bad59af4db12 (patch) | |
tree | f9bf767d79bc204a7e18ab7d9ca48f9b83c045a5 /drivers | |
parent | 1a1d6c3c8ce2022462ca9b56fde45ffb69821690 (diff) | |
download | lwn-13f09b941bc8cfb1a1355a26c999bad59af4db12.tar.gz lwn-13f09b941bc8cfb1a1355a26c999bad59af4db12.zip |
drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
commit f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 upstream.
According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.
v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)
Cc: Bjoern C <lkml@call-home.ch>
Cc: Alexandru DAMIAN <alexandru.damian@intel.com>
Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[bwh: Backported to 3.2: adjust context]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 61b708b60faa..2ea8a96e0f14 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7252,6 +7252,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev, goto err_unpin; } + /* + * BSpec MI_DISPLAY_FLIP for IVB: + * "The full packet must be contained within the same cache line." + * + * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same + * cacheline, if we ever start emitting more commands before + * the MI_DISPLAY_FLIP we may need to first emit everything else, + * then do the cacheline alignment, and finally emit the + * MI_DISPLAY_FLIP. + */ + ret = intel_ring_cacheline_align(ring); + if (ret) + goto err_unpin; + ret = intel_ring_begin(ring, 4); if (ret) goto err_unpin; |