diff options
| author | David Woodhouse <David.Woodhouse@intel.com> | 2010-06-15 10:57:57 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-05-09 15:55:37 -0700 |
| commit | 400036c2e53672323a7dd743146017995ffecb27 (patch) | |
| tree | 0ae1e27cee7908ca947e8a86fde3cc684927e485 /drivers | |
| parent | e281433b151dad34ac1556adc5d276e4cf077b43 (diff) | |
| download | lwn-400036c2e53672323a7dd743146017995ffecb27.tar.gz lwn-400036c2e53672323a7dd743146017995ffecb27.zip | |
intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions.
commit 2d9e667efdfb4e986074d98e7d9a424003c7c43b upstream.
Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.
Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/intel-iommu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c index b643a2d0f6d8..5b680dfd871e 100644 --- a/drivers/pci/intel-iommu.c +++ b/drivers/pci/intel-iommu.c @@ -382,7 +382,7 @@ int dmar_disabled = 0; int dmar_disabled = 1; #endif /*CONFIG_DMAR_DEFAULT_ON*/ -static int __initdata dmar_map_gfx = 1; +static int dmar_map_gfx = 1; static int dmar_forcedac; static int intel_iommu_strict; @@ -3741,6 +3741,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) */ printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); rwbf_quirk = 1; + + /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */ + if (dev->revision == 0x07) { + printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); + dmar_map_gfx = 0; + } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |