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authorNava kishore Manne <nava.manne@xilinx.com>2022-04-23 22:32:34 +0530
committerXu Yilun <yilun.xu@intel.com>2022-05-10 16:04:50 +0800
commitbaf7d27d033c7cbbdd483ce0867b27e54b702ad5 (patch)
tree7234c2e13323893efdc43aa3518a84c60900f948 /drivers
parent3f3f9cb67f69a45d2fa52b919c1e6bc6416b9ec7 (diff)
downloadlwn-baf7d27d033c7cbbdd483ce0867b27e54b702ad5.tar.gz
lwn-baf7d27d033c7cbbdd483ce0867b27e54b702ad5.zip
fpga: Use tab instead of space indentation
In FPGA Makefile has both space and tab indentation, to make them align use tab instead of space indentation. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Link: https://lore.kernel.org/r/20220423170235.2115479-5-nava.manne@xilinx.com Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/fpga/Makefile6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 0bff783d1b61..5935b3d0abd5 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,9 +18,9 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
-obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
# FPGA Bridge Drivers
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o