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authorBiju Das <biju.das.jz@bp.renesas.com>2024-08-30 21:30:03 +0100
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2024-08-31 07:30:32 +0200
commit84d1078af52f6a099267fccfb1dda602ac8b66d0 (patch)
tree3178048a2e13c00d0f4dccf9c0d7c47170fc4e02 /drivers
parentff390189b7f2cfa20c644bc58b4462b5e2621838 (diff)
downloadlwn-84d1078af52f6a099267fccfb1dda602ac8b66d0.tar.gz
lwn-84d1078af52f6a099267fccfb1dda602ac8b66d0.zip
memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins
The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL SMARC EVK uses Renesas AT25QL128A flash. With current pin setting for IOVF pin, 4-bit flash write fails for AT25QL128A flash. Use Hi-Z state as the default for IOVF pin, so that spi controller driver in linux will be independent of flash type. To support this, during board production, the bit 4 of the NV config register must be cleared by the bootloader for Micron flash. Output from u-boot after clearing bit4 of NVCR register. => renesas_micron_flash_nvcr SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB NVCR=0xef Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20240830203014.199326-2-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/memory/renesas-rpc-if.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 3167826b236a..7fbd36fa1a1b 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -367,7 +367,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash)
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
RPCIF_CMNCR_BSZ(3),
- RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
+ RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) |
RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
else
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,