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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2014-01-30 00:19:36 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-01-30 12:58:41 +0100 |
| commit | 654c90c67853c4f2677af36b154304b7d560aef8 (patch) | |
| tree | 4298b70d20fad9d97aaf03178494f47d87082d70 /drivers | |
| parent | 1d762aad7bcc93ae739008e98a9dc8e5cbce565e (diff) | |
| download | lwn-654c90c67853c4f2677af36b154304b7d560aef8.tar.gz lwn-654c90c67853c4f2677af36b154304b7d560aef8.zip | |
drm/i915: Logically reorder error register capture
Create logical sections in an attempt to clean up, and continue to keep
future additions clean.
v2: Reworded the comments. Added section headers (Chris)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gpu_error.c | 59 |
1 files changed, 36 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index d34290be1081..4cc29bd8e60e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -985,41 +985,54 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, struct drm_device *dev = dev_priv->dev; int pipe; - error->eir = I915_READ(EIR); - error->pgtbl_er = I915_READ(PGTBL_ER); - if (HAS_HW_CONTEXTS(dev)) - error->ccid = I915_READ(CCID); + /* General organization + * 1. Registers specific to a single generation + * 2. Registers which belong to multiple generations + * 3. Feature specific registers. + * 4. Everything else + * Please try to follow the order. + */ - if (HAS_PCH_SPLIT(dev)) - error->ier = I915_READ(DEIER) | I915_READ(GTIER); - else if (IS_VALLEYVIEW(dev)) + /* 1: Registers specific to a single generation */ + if (IS_VALLEYVIEW(dev)) { error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); - else if (IS_GEN2(dev)) - error->ier = I915_READ16(IER); - else - error->ier = I915_READ(IER); + error->forcewake = I915_READ(FORCEWAKE_VLV); + } - if (INTEL_INFO(dev)->gen >= 6) - error->derrmr = I915_READ(DERRMR); + if (IS_GEN7(dev)) + error->err_int = I915_READ(GEN7_ERR_INT); - if (IS_VALLEYVIEW(dev)) - error->forcewake = I915_READ(FORCEWAKE_VLV); - else if (INTEL_INFO(dev)->gen >= 7) - error->forcewake = I915_READ(FORCEWAKE_MT); - else if (INTEL_INFO(dev)->gen == 6) + if (IS_GEN6(dev)) error->forcewake = I915_READ(FORCEWAKE); - if (!HAS_PCH_SPLIT(dev)) - for_each_pipe(pipe) - error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); + if (IS_GEN2(dev)) + error->ier = I915_READ16(IER); + + /* 2: Registers which belong to multiple generations */ + if (INTEL_INFO(dev)->gen >= 7) + error->forcewake = I915_READ(FORCEWAKE_MT); if (INTEL_INFO(dev)->gen >= 6) { + error->derrmr = I915_READ(DERRMR); error->error = I915_READ(ERROR_GEN6); error->done_reg = I915_READ(DONE_REG); } - if (INTEL_INFO(dev)->gen == 7) - error->err_int = I915_READ(GEN7_ERR_INT); + /* 3: Feature specific registers */ + if (HAS_HW_CONTEXTS(dev)) + error->ccid = I915_READ(CCID); + + if (HAS_PCH_SPLIT(dev)) + error->ier = I915_READ(DEIER) | I915_READ(GTIER); + else { + error->ier = I915_READ(IER); + for_each_pipe(pipe) + error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); + } + + /* 4: Everything else */ + error->eir = I915_READ(EIR); + error->pgtbl_er = I915_READ(PGTBL_ER); i915_get_extra_instdone(dev, error->extra_instdone); } |