diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-12-14 18:25:32 +0530 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2023-12-18 20:44:17 -0500 |
| commit | 26cdd6940c94cbd81cc524093bd689b061df58c4 (patch) | |
| tree | 0a540ac9f7e15ded4316d94fb700183d898fe12a /drivers/ufs | |
| parent | 24db9626baedf9520f13af58cc5c02756721ec04 (diff) | |
| download | lwn-26cdd6940c94cbd81cc524093bd689b061df58c4.tar.gz lwn-26cdd6940c94cbd81cc524093bd689b061df58c4.zip | |
scsi: ufs: qcom: Fix ESI vector mask
While cleaning up the code to use ufshcd_rmwl() helper, the ESI vector mask
was changed incorrectly. Fix it and also define a proper macro for the
value together with FIELD_PREP().
Reported-by: Andrew Halaney <ahalaney@redhat.com>
Fixes: 0e9f4375db1c ("scsi: ufs: qcom: Use ufshcd_rmwl() where applicable")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231214125532.55109-1-manivannan.sadhasivam@linaro.org
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs')
| -rw-r--r-- | drivers/ufs/host/ufs-qcom.c | 4 | ||||
| -rw-r--r-- | drivers/ufs/host/ufs-qcom.h | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index d5cca5d3a98f..9fd8d737edea 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1744,7 +1744,9 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba) } else { if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && host->hw_ver.step == 0) - ufshcd_rmwl(hba, ESI_VEC_MASK, 0x1f00, REG_UFS_CFG3); + ufshcd_rmwl(hba, ESI_VEC_MASK, + FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1), + REG_UFS_CFG3); ufshcd_mcq_enable_esi(hba); } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9026fe243307..9dd9a391ebb7 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -15,6 +15,7 @@ #define HBRN8_POLL_TOUT_MS 100 #define DEFAULT_CLK_RATE_HZ 1000000 #define MAX_SUPP_MAC 64 +#define MAX_ESI_VEC 32 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) |