diff options
| author | Zhang Rui <rui.zhang@intel.com> | 2022-11-08 16:12:19 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-11-09 14:58:02 +0100 |
| commit | be6abd3ed65678f8c7bd212808a9841785c2d5ca (patch) | |
| tree | a8e8f36218a61bc02c939fa0d22fd818de309db8 /drivers/thermal | |
| parent | 54d9135cf223f221546bd51b0f5e4a73e99891f4 (diff) | |
| download | lwn-be6abd3ed65678f8c7bd212808a9841785c2d5ca.tar.gz lwn-be6abd3ed65678f8c7bd212808a9841785c2d5ca.zip | |
thermal: intel: intel_tcc_cooling: Detect TCC lock bit
When MSR_IA32_TEMPERATURE_TARGET is locked, TCC Offset can not be
updated even if the PROGRAMMABE Bit is set.
Yield the driver on platforms with MSR_IA32_TEMPERATURE_TARGET locked.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/thermal')
| -rw-r--r-- | drivers/thermal/intel/intel_tcc_cooling.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 95adac427b6f..c9e84e615fce 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -14,6 +14,7 @@ #define TCC_SHIFT 24 #define TCC_MASK (0x3fULL<<24) #define TCC_PROGRAMMABLE BIT(30) +#define TCC_LOCKED BIT(31) static struct thermal_cooling_device *tcc_cdev; @@ -108,6 +109,15 @@ static int __init tcc_cooling_init(void) if (!(val & TCC_PROGRAMMABLE)) return -ENODEV; + err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); + if (err) + return err; + + if (val & TCC_LOCKED) { + pr_info("TCC Offset locked\n"); + return -ENODEV; + } + pr_info("Programmable TCC Offset detected\n"); tcc_cdev = |