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| author | Krishna Yarlagadda <kyarlagadda@nvidia.com> | 2023-02-23 21:56:34 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-02-23 17:28:56 +0000 |
| commit | f7482d8285b638be87a594a30edaaf1341135c1a (patch) | |
| tree | f1fc6bef5a3a31bfb162c0998f9d649d363426a6 /drivers/spi | |
| parent | 078a5517d22342eb0474046d3e891427a2552e3c (diff) | |
| download | lwn-f7482d8285b638be87a594a30edaaf1341135c1a.tar.gz lwn-f7482d8285b638be87a594a30edaaf1341135c1a.zip | |
spi: tegra210-quad: set half duplex flag
Tegra QSPI controller only supports half duplex transfers.
Set half duplex constrain flag.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/20230223162635.19747-3-kyarlagadda@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-tegra210-quad.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 9f356612ba7e..258e3b8c9c2c 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1532,6 +1532,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_CONTROLLER_HALF_DUPLEX; master->setup = tegra_qspi_setup; master->transfer_one_message = tegra_qspi_transfer_one_message; master->num_chipselect = 1; |