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| author | Alexander Kochetkov <al.kochet@gmail.com> | 2016-03-06 13:04:17 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-03-06 18:36:13 +0700 |
| commit | 0277e01aebc8895198a4717ccaf7e4fcf39ada78 (patch) | |
| tree | ae922954695c781e170436c8cb313c54c6aefb90 /drivers/spi | |
| parent | b920cc3191d7612f26f36ee494e05b5ffd9044c0 (diff) | |
| download | lwn-0277e01aebc8895198a4717ccaf7e4fcf39ada78.tar.gz lwn-0277e01aebc8895198a4717ccaf7e4fcf39ada78.zip | |
spi/rockchip: fix endian mode for 16-bit transfers
16-bit transfers must be in big endian mode on wire.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-rockchip.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 6cdb4d81d66c..9a5c51764833 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs) int rsd = 0; u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) - | (CR0_SSD_ONE << CR0_SSD_OFFSET); + | (CR0_SSD_ONE << CR0_SSD_OFFSET) + | (CR0_EM_BIG << CR0_EM_OFFSET); cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); |